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  11- /1 4- bit, 2.5 gsps, rf digital - to - analog converters data sheet ad9737a / AD9739A rev. information furnis hed by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject t o change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 - 2012 analog devices, inc. all rights reserved. features direct rf synthesis at 2.5 gsps update rate dc to 1.25 ghz in baseband mode 1.25 ghz to 3.0 ghz in mix - mode industry leading single/multicarrier if or rf synthesis dual - port lvds data interface up to 1.25 gsps operation source synchronous ddr cl ocking pin compatible with the ad9739 programmable output current: 8.7 ma to 31.7 ma low power: 1.1 w at 2.5 gsps applications broadband communications systems docsis cmts systems military jammers instrumentation, automatic test equipment radar, avionics functional block dia gram lvds ddr receiver dci sdo sdio sclk cs dacclk dco db0[13:0] db1[13:0] clk distribution (div-by-4) data controller 4-to-1 data assembler spi reset dll (mu controller) lvds ddr receiver data latch ioutn ioutp vref i120 irq 1.2v dac bias ad9737a/AD9739A txdac core 09616-001 figure 1 . general description the ad9737a / AD9739A a re 11- bit and 1 4- bit , 2.5 gsps high performance rf dac s that are capable of synthesizing wideband signals from dc up to 3 ghz. the ad9737a / AD9739A are pin and fu nctionally compatible with the ad9739 with the exception that the ad9737a / AD9739A do not support synchronization or rz mode, and are specified to operate between 1.6 gsps an d 2.5 gsps. by elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the ad9737a / ad9739 a between power - up cycles, thus allowing for possible system calibration. ac linearity and noise performance remain the same between the ad9739 and the ad9737a / AD9739A . the inclusion of on - chip controllers simplifies syst em integ ration. a dual - port, source synchronous, lvds interface simplifies the digital interface with existing fgpa/asic technology. on - chip controlle rs are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the dac core. a serial peripheral inter face (spi) is used for device configuration as well as readback of status register s. the ad9737a / AD9739A are manufactured on a 0.18 m cmos process and operate from 1.8 v and 3.3 v supplies. they are supplied in a 160- ball chip scale ball grid array for reduced package parasitics. product highlights 1. ability to synthesize high quality wideband signals with bandwidths of up to 1.25 ghz in the first or second nyquist zone. 2. a proprietary quad - switch dac architecture provides exceptional ac linearity performance while enabling mix - mode operation. 3. a dual - port, double data rate, lvds interface supports the maximum conversion rate of 2500 msps. 4. on- chip controllers manage external and internal clock domain skews. 5. programmable differential current output with an 8.66 ma to 31.66 ma range. c
ad9737a/AD9739A data sheet rev. | page 2 of 64 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 lvds digital specifications ........................................................ 5 serial port specifications ............................................................. 6 ac specifications .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ad9737a ..................... 14 static l in earity ............................................................................ 14 ac (normal mode) .................................................................... 15 ac (mix - mode) .......................................................................... 17 one - carrier docsis performance (normal mode) ............ 20 four - carrier docsis performance (normal mode) ........... 21 eight - carrier docsis performance (normal mode) .......... 22 16- carrier docsis performance (normal mode) ............... 23 32- carrier docsis performance (normal mode) ............... 24 64 - and 128 - carrier docsis performance (normal mode) 25 typical performance characteristics AD9739A ..................... 26 static linearity ............................................................................ 26 ac (normal mode) .................................................................... 28 ac (mix - mode) .......................................................................... 31 one - carrier docsis performance (normal mode) ............ 33 four - carrier docsis performance (normal mode) ........... 34 eight - carrier docsis performanc e (normal mode) .......... 35 16- carrier docsis performance (normal mode) ............... 36 32- carrier docsis performance (normal mode) ............... 37 64 - and 128 - carrier docsis performance (normal mode) 38 terminology .................................................................................... 39 serial p ort interface (spi) register ............................................... 40 spi register map description .................................................. 40 spi operation ............................................................................. 40 spi register map ............................................................................ 42 spi port configuration and software reset ........................... 43 power - down lvds interface and txdac? ........................... 43 controller clock disable ........................................................... 43 interrupt request (irq) enable/status ................................... 44 t xdac full - scale current setting (i outfs ) and sleep ........... 44 txdac quad - switch mode of operation .............................. 44 dci phase alignment status .................................................... 44 data receiver controller configuration ................................. 44 dat a receiver controller_data sample delay value ............ 45 data receiver controller_dci delay value/window and phase rotation ............................................................................ 45 data receiver controller_delay line status .......................... 45 data receiver controller lock/tracking status ..................... 45 clk input common mode ...................................................... 46 mu controller configuration and status ................................ 46 part id ......................................................................................... 47 theory of operation ...................................................................... 48 lvds data port interface .......................................................... 49 mu controller ............................................................................. 52 interrupt requests ...................................................................... 54 analog interface considera tions .................................................. 55 analog modes of operation ..................................................... 55 clock input considerations ...................................................... 56 voltage reference ....................................................................... 57 analog outputs .......................................................................... 57 output stage configuration ..................................................... 59 nonideal spectral artifacts ....................................................... 60 lab evaluation of the ad9737a/AD9739A ........................... 61 recommended start - up sequence .......................................... 61 outline dimensions ....................................................................... 63 ordering guide .......................................................................... 63 c
data sheet ad9737a/AD9739A rev. c | page 3 of 64 revision history 2/12rev. b to rev. c changes to figure 5 ........................................................................... 9 changes to table 7 .......................................................................... 11 changes to ordering guide ........................................................... 63 2/12rev. a to rev. b added ad9737a ................................................................ universal reorganized layout ........................................................... universal moved revision history section ..................................................... 3 deleted 6% from table summary statement; changes to table 1 ............................................................................................ 4 deleted 6% from table summary statement, table 2 ................ 5 deleted 6% from table summary statement, table 3 ................ 6 changes to ac specifications section and table 4 ....................... 7 added figure 5, renumbered sequentially ................................... 9 added figure 7 and table 7, renumbered sequentially ............ 10 deleted figure 24 ............................................................................ 13 added typical performance characteristicsad9737a section and figure 9 to figure 77 ................................................. 14 deleted table 9 ................................................................................ 25 added static linearity section and figure 78 to figure 88 ............ 26 added figure 106 ............................................................................ 30 changes to figure 116, figure 117, figure 118, figure 119, figure 120, and figure 121 ............................................................. 33 changes to figure 122, figure 123, figure 124, figure 125, figure 126, and figure 127 ............................................................. 34 changes to figure 128, figure 129, figure 130, figure 131, figure 132, and figure 133 ............................................................. 35 changes to figure 134, figure 135, figure 136, figure 137, figure 138, and figure 139 ............................................................. 36 changes to figure 140, figure 141, figure 142, figure 143, figure 144, and figure 145 ............................................................. 37 changes to figure 146, figure 147, figure 148, figure 149, and figure 150; added figure 151 ................................................ 38 added table 10 ................................................................................ 42 added spi port configuration and software reset section, power-down lvds interface and txdac section, controller clock disable section, and table 11 to table 13 ........................ 43 added interrupt request (irq) enable/status section, txdac full-scale current setting (i outfs ) and sleep section, txdac quad-switch mode of operation section, dci phase alignment status section, data receiver controller configuration section, and table 14 to table 18 ........................ 44 added data receiver controller_data sample delay value section, data receiver controller_dci delay value/window and phase rotation section, data receiver controller_delay line status section, data receiver controller lock/tracking status section, and table 19 to table 22 ...................................... 45 added clk input common mode section, and mu controller configuration and status section, and table 23 and table 24 ..................................................................................... 46 added part id section, and table 25 ........................................... 47 changes to lvds data port interface section ............................ 49 changes to data receiver controller initialization description section ........................................................................ 51 changes to mu controller section ............................................... 52 added figure 167 and table 27, changes to mu controller initialization description section ................................................. 53 changes to analog modes of operation section, figure 171, and figure 172 ................................................................................. 55 updated outline dimensions ........................................................ 63 changes to ordering guide ........................................................... 63 7/11rev. 0 to rev. a changed maximum update rate (dacclk input) parameter to dac clock rate parameter in table 4 ....................................... 6 added adjusted dac update rate parameter and endnote 1 in table 4 ................................................................................................. 6 updated outline dimensions ........................................................ 43 1/11revision 0: initial version
ad9737a/AD9739A data sheet rev. | page 4 of 64 specifications dc specifications vdda = vdd33 = 3.3 v, vddc = vdd = 1.8 v, i outfs = 20 ma. table 1. ad9737a AD9739A parameter min typ max min typ max unit resolution 11 14 bits accuracy integral nonlinearity (inl) 0.5 2.5 lsb differential nonlinearity (dnl) 0.5 2.0 lsb analog outputs gain error (with internal reference) 5.5 5.5 % full - scale output current 8.66 20.2 31.66 8.66 20.2 31.66 ma output compliance range ? 1.0 +1.0 ? 1.0 +1.0 v common - mode output resistance 10 10 m? differential output resistance 70 70 ? output capacitance 1 1 pf dac clock input (dacclk_p, dacclk_n) differential peak -to - peak voltage 1.2 1.6 2.0 1.2 1.6 2.0 v common - mode voltage 900 900 mv clock rate 1.6 2.5 1.6 2.5 ghz temperature drift gain 60 60 ppm/c reference voltage 20 20 ppm/c reference internal reference voltage 1.15 1.2 1.25 1.15 1.2 1.25 v output resistance 5 5 k? analog supply voltages vdda 3.1 3.3 3.5 3.1 3.3 3.5 v vddc 1.70 1.8 1.90 1.70 1.8 1.90 v digital supply voltages vdd33 3.10 3.3 3.5 3.10 3.3 3.5 v vdd 1.70 1.8 1.90 1.70 1.8 1.90 v supply currents and power di ssipation, 2.0 gsps i vdda 37 38 37 38 ma i vddc 158 167 158 167 ma i vdd33 14.5 16 14.5 16 ma i vdd 173 183 173 183 ma power dissipation 0.770 0.770 w sleep mode, i vdda 2.5 2.75 2.5 2.75 ma power - down mode (all power - down bits set in register 0x01 and register 0x02) i vdda 0.02 0.02 ma i vddc 6 6 ma i vdd33 0.6 0.6 ma i vdd 0.1 0.1 ma supply currents and power dissipation, 2.5 gsps i vddc 223 223 ma i vdd33 14.5 14.5 ma i vdd 21 5 215 ma power dissipation 0.960 0.960 mw c
data sheet ad9737a/AD9739A rev. | page 5 of 64 lvds digital specifi cations vdda = vdd33 = 3.3 v, vddc = vdd = 1.8 v, i outfs = 20 ma. lvds drivers and receivers are compliant to the ieee standard 1596.3 - 1996 reduced range link, unless otherwise not ed. table 2. parameter min typ max unit lvds data inputs (db0[13:0], db1[13:0]) 1 input common - mode voltage range, v com 825 1575 mv logic high differential input threshold, v ih_dth 175 400 mv logic low differential input threshold, v il_dth ?175 ?400 mv receiver differential input impedance, r in 80 120 ? input capacitance 1.2 pf lvds input rate 1250 msps lvds minimum data valid period (t mde ) (see figure 159 ) 344 ps l vds clock input (dci) 2 input common - mode voltage range, v com 825 1575 mv logic high differential input threshold, v ih_dth 175 400 mv logic low differential input threshold, v il_dth ?175 ?400 mv receiver differential input impedance, r in 80 120 ? input capacitance 1.2 pf maximum clock rate 625 mhz lvds clock output (dco) 3 output voltage high (dco_p or dco_n) 1375 mv output voltage low (dco_p or dco_n) 1025 mv output differential voltage, |v od | 150 200 250 mv output offset volt age, v os 1150 1250 mv output impedance, single - ended, r o 80 100 120 ? r o single - ended mismatch 10 % maximum clock rate 625 mhz 1 db0[x]p, db0[x]n, db1[x]p, and db1[x]n pins. 2 dci_p and dci_n pins. 3 dco_p and dco_n pins with 100 ? diff erential termination. c
ad9737a/AD9739A data sheet rev. | page 6 of 64 serial port specifications vdda = vdd33 = 3.3 v, vddc = vdd = 1.8 v. table 3 . parameter min typ max unit write operation (see figure 154) sclk clock rate, f sclk , 1/t sclk 20 mhz sclk clock high, t high 18 ns sclk clock low, t low 18 ns sdio to sclk setup time, t ds 2 ns sclk to sdio hold ti me, t dh 1 ns cs to sclk setup time, t s 3 ns sclk to cs hold time, t h 2 ns read operation (see figure 155 and figure 156 ) sc lk clock rate, f sclk , 1/t sclk 20 mhz sclk clock high, t high 18 ns sclk clock low, t low 18 ns sdio to sclk setup time, t ds 2 ns sclk to sdio hold time, t dh 1 ns cs to sclk setup time, t s 3 ns sclk to sdio (or sdo) data valid time, t dv 15 ns cs to sdio (or sdo) output valid to high -z, t ez 2 ns inputs (sdi, sdio, sclk, cs ) voltage in high, v ih 2.0 3.3 v voltage in low, v il 0 0.8 v current in high, i ih ?10 +10 a current in low, i il ?10 +10 a output (sdio) voltage out high, v oh 2.4 3.5 v voltage out low, v ol 0 0.4 v current out high, i oh 4 ma current out low, i ol 4 ma c
data sheet ad9737a/AD9739A rev. | page 7 of 64 ac specifications vdda = vdd33 = 3.3 v, vddc = vdd = 1.8 v, i outfs = 20 ma, f dac = 2400 msps, unless otherwise noted. table 4. ad9737a AD9739A parameter min typ max min typ max unit dynamic performance dac clock rate 1600 2500 1600 2500 msps adjusted dac update rate 1 1600 2500 1600 2500 msps output settling time to 0.1% 13 13 ns spurious-free dynamic range (sfdr) f out = 100 mhz 70 70 dbc f out = 350 mhz 65 65 dbc f out = 550 mhz 58 58 dbc f out = 950 mhz 55 55 dbc two-tone intermodulation distortion (imd), f out2 = f out1 + 1.25 mhz f out = 100 mhz 94 94 dbc f out = 350 mhz 78 78 dbc f out = 550 mhz 72 72 dbc f out = 950 mhz 68 68 dbc noise spectral density (nsd), 0 dbfs single tone f out = 100 mhz ?162 ?167 dbm/hz f out = 350 mhz ?162 ?166 dbm/hz f out = 550 mhz ?161 ?164 dbm/hz f out = 850 mhz ?161 ?163 dbm/hz wcdma aclr (single carrier), adjacent/alternate adjacent channel f dac = 2457.6 msps, f out = 350 mhz 80/81 80/80 dbc f dac = 2457.6 msps, f out = 950 mhz 75/75 78/79 dbc f dac = 2457.6 msps, f out = 1700 mhz (mix-mode) 69/71 74/74 dbc f dac = 2457.6 msps, f out = 2100 mhz (mix-mode) 66/67 69/72 dbc 1 adjusted dac updated rate is calculated as f dac divided by the minimum required i nterpolation factor. for the ad9737a/AD9739A, the minimum interpolation factor is 1. thus, with f dac = 2500 msps, f dac , adjusted, = 2500 msps. c
ad9737a/AD9739A data sheet rev. | page 8 of 64 absolute maximum rat ings table 5. parameter rating vdda to vssa ? 0.3 v to +3.6 v vdd33 to vss ? 0.3 v to +3.6 v vdd to vss ? 0.3 v to +1.98 v vddc to vssc ? 0.3 v to +1.98 v vssa to vss ? 0.3 v to +0.3 v vssa to vssc ? 0.3 v to +0.3 v vss to vssc ? 0.3 v to +0.3 v dacclk_p, dacclk_n to vssc ? 0.3 v to vddc + 0.18 v dc i, dco to vss ? 0.3 v to vdd33 + 0.3 v lvds data inputs to vss ? 0.3 v to vdd33 + 0.3 v ioutp, ioutn to vssa ? 1.0 v to vdda + 0.3 v i120, vref to vssa ? 0.3 v to vdda + 0.3 v i rq, cs , sclk, sdo, sdio, reset to vss ? 0.3 v to vdd33 + 0.3 v junction temperature 150c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - ca se conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 160- ball csp_bga 31.2 7.0 c/w 1 1 with no airflow movement. esd caution c
data sheet ad9737a/AD9739A rev. c | page 9 of 64 pin configurations and function descriptions 09616-002 ad9737a/AD9739A 1413 12 11 10 876 32 19 54 a b c d e f g h j k l m n p vssa, analog supply ground vssa shield, analog supply ground shield vdda, 3.3v, analog supply figure 2. analog supply pins (top view) a b c d e f g h j k l m n p 1413 12 11 10 876 32 19 54 vss digital supply ground vdd33, 3.3v digital supply vdd, 1.8v, digital supply 09616-003 ad9737a/AD9739A figure 3. digital supply pins (top view) a b c d e f g h j k l m n p 141312 11 10 876 32 19 54 vssc, clock supply ground vddc, 1.8v, clock supply 09616-004 ad9737a/AD9739A figure 4. digital lvds clock supply pins (top view) a b e f g h j k l db1[0:10]p m db1[0:10]n c dacclk_n d dacclk_p db0[0:10]p n db0[0:10]n p 14 13 121110 876 32 19 54 differential input signal (clock or data) dci_p/_n dco_p/_n 09616-036 ad9737a figure 5. ad9737a digital lvds input, clock i/o (top view) a b c d e f g h j k l m db1[0:13]p db1[0:13]n db0[0:13]p db0[0:13]n differential input signal (clock or data) dacclk_n dacclk_p n p 141312 11 10 876 32 19 54 dci_p/_n dco_p/_n 09616-005 AD9739A figure 6. AD9739A digital lvds input, clock i/o (top view)
ad9737a/AD9739A data sheet rev. | page 10 of 64 a b c d e f g h j k l m n p 141312 11 10 6 321 9 54 irq cs sclk reset sdio sdo 7 ioutn 8 iout p i120 vref 09616-006 ad9737 a figure 7 . ad9737a analog i/o and spi control pins (top view) table 7 . ad9737a pin functi on description s pin no. mnemonic description c1, c2, d1, d2, e1, e2, e3, e4 vddc 1.8 v clock supply input. a1, a2, a3, a4, a5, b1, b2, b3, b4, b5, c4, c5, d4, d5 vssc clock supply ground . a10, a1 1, b10, b11, c10, c11, d10, d11 vdda 3.3 v analog suppl y input. a12, a13, b12, b13, c12, c13, d12, d13, vssa analog supply ground . a6, a9, b6, b9, c6, c9, d6, d9, e11, e12, e13, e14, f1, f2, f3, f 4, f11, f12 vssa shield analog supply ground shield. tie to vssa at the dac. a14 nc do not connect to this pin. a7, b7, c7, d7 ioutn dac negative current output source. a8, b8, c8, d8 ioutp dac positive current output source. b14 i120 nominal 1.2 v reference. tie to analog ground via a 10 k? resistor to gener ate a 120 a reference current. c14 vref voltage reference input/output. decouple to vssa with a 1 nf capacitor. d14 nc factory test pin. do not connect to this pin. c3, d3 dacclk_n/dacclk_p negative/pos itive dac clock input (d acclk). f13 irq interrupt request open drain output. active high. pull up to vdd33 with a 10 k? resistor. f14 reset reset input. active high. tie to vss if unused. g13 cs serial port enable input. g14 sdio serial port data input/outpu t. h13 sclk serial port clock input. h14 sdo serial port data output. j3, j4, j11, j12 vdd33 3.3 v digital supply input. g1, g2, g3, g4, g11, g12 vdd 1.8 v digital supply input. h1, h2, h3, h4, h11, h12, k3, k4, k11, k12 vss digital supply ground . j1 , j2 nc dif ferential resistor of 200 ? exis ts between j1 and j2. do not connect to th i s pin. k1, k2 nc di fferential resistor of 100 ? ex ists between k1 and k2. do not connect to th i s pin. j13, j14 dco_p/dco_n positive/ne gative data clock output (dco). k13, k14 dci_p/dci_n positive/n egative data clock input (dci). c
data sheet ad9737a/AD9739A rev. c | page 11 of 64 pin no. mnemonic description l1, m1 nc, nc do not connect to this pin. l2, m2 nc, nc do not connect to this pin. l3, m3 nc, nc do not connect to this pin. l4, m4 db1[0]p/db1[0]n port 1 posi tive/negative data input bit 0. l5, m5 db1[1]p/db1[1]n port 1 posi tive/negative data input bit 1. l6, m6 db1[2]p/db1[2]n port 1 posi tive/negative data input bit 2. l7, m7 db1[3]p/db1[3]n port 1 posi tive/negative data input bit 3. l8, m8 db1[4]p/db1[4]n port 1 posi tive/negative data input bit 4. l9, m9 db1[5]p/db1[5]n port 1 posi tive/negative data input bit 5. l10, m10 db1[6]p/db1[6]n port 1 po sitive/negative data input bit 6. l11, m11 db1[7]p/db1[7]n port 1 po sitive/negative data input bit 7. l12, m12 db1[8]p/db1[8]n port 1 po sitive/negative data input bit 8. l13, m13 db1[9]p/db1[9]n port 1 po sitive/negative data input bit 9. l14, m14 db1[10]p/db1[10]n port 1 positive/negative data input bit 10. n1, p1 nc, nc do not connect to this pin. n2, p2 nc, nc do not connect to this pin. n3, p3 nc, nc do not connect to this pin. n4, p4 db0[0]p/db0[0]n port 0 posi tive/negative data input bit 0. n5, p5 db0[1]p/db0[1]n port 0 posi tive/negative data input bit 1. n6, p6 db0[2]p/db0[2]n port 0 posi tive/negative data input bit 2. n7, p7 db0[3]p/db0[3]n port 0 posi tive/negative data input bit 3. n8, p8 db0[4]p/db0[4]n port 0 posi tive/negative data input bit 4. n9, p9 db0[5]p/db0[5]n port 0 posi tive/negative data input bit 5. n10, p10 db0[6]p/db0[6]n port 0 po sitive/negative data input bit 6. n11, p11 db0[7]p/db0[7]n port 0 po sitive/negative data input bit 7. n12, p12 db0[8]p/db0[8]n port 0 po sitive/negative data input bit 8. n13, p13 db0[9]p/db0[9]n port 0 po sitive/negative data input bit 9. n14, p14 db0[10]p/db0[10]n port 0 positive/negative data input bit 10.
ad9737a/AD9739A data sheet rev. c | page 12 of 64 a b c d e f g h j k l m n p 14 1312 11 10 6 32 19 54 irq cs sclk reset sdio sdo 7 ioutn 8 ioutp i120 vref 09616-037 AD9739A figure 8. AD9739A analog i/o and spi control pins (top view) table 8 . AD9739A pin function descriptions pin no. mnemonic description c1, c2, d1, d2, e1, e2, e3, e4 vddc 1.8 v clock supply input. a1, a2, a3, a4, a5, b1, b2, b3, b4, b5, c4, c5, d4, d5 vssc clock supply ground. a10, a11, b10, b11, c10, c11, d10, d 11 vdda 3.3 v analog supply input. a12, a13, b12, b13, c12, c13, d12, d13, vssa analog supply ground. a6, a9, b6, b9, c6, c9, d6, d9, e11, e12, e13, e14, f1, f2, f3, f4, f11, f12 vssa shield analog supply ground shield. tie to vssa at the dac. a14 nc do not connect to this pin. a7, b7, c7, d7 ioutn dac negative current output source. a8, b8, c8, d8 ioutp dac positive current output source. b14 i120 nominal 1.2 v reference. tie to analog ground via a 10 k resistor to generate a 120 a reference current. c14 vref voltage reference input/output. decouple to vssa with a 1 nf capacitor. d14 nc factory test pin. do not connect to this pin. c3, d3 dacclk_n/dacclk_p negative/positive dac clock input (dacclk). f13 irq interrupt request open drain output. active high. pull up to vdd33 with a 10 k resistor. f14 reset reset input. active high. tie to vss if unused. g13 cs serial port enable input. g14 sdio serial port data input/output. h13 sclk serial port clock input. h14 sdo serial port data output. j3, j4, j11, j12 vdd33 3.3 v digital supply input. g1, g2, g3, g4, g11, g12 vdd 1.8 v digital supply input. h1, h2, h3, h4, h11, h12, k3, k4, k11, k12 vss digital supply ground. j1, j2 nc differential resistor of 200 ex ists between j1 and j2. do not connect to this pin. k1, k2 nc differential resistor of 100 ex ists between k1 and k2. do not connect to this pin. j13, j14 dco_p/dco_n positive/negative data clock output (dco). k13, k14 dci_p/dci_n positive/negative data clock input (dci).
data sheet ad9737a/AD9739A rev. c | page 13 of 64 pin no. mnemonic description l1, m1 db1[0]p/db1[0]n port 1 posi tive/negative data input bit 0. l2, m2 db1[1]p/db1[1]n port 1 posi tive/negative data input bit 1. l3, m3 db1[2]p/db1[2]n port 1 posi tive/negative data input bit 2. l4, m4 db1[3]p/db1[3]n port 1 posi tive/negative data input bit 3. l5, m5 db1[4]p/db1[4]n port 1 posi tive/negative data input bit 4. l6, m6 db1[5]p/db1[5]n port 1 posi tive/negative data input bit 5. l7, m7 db1[6]p/db1[6]n port 1 posi tive/negative data input bit 6. l8, m8 db1[7]p/db1[7]n port 1 posi tive/negative data input bit 7. l9, m9 db1[8]p/db1[8]n port 1 posi tive/negative data input bit 8. l10, m10 db1[9]p/db1[9]n port 1 posi tive/negative data input bit 9. l11, m11 db1[10]p/db1[10]n port 1 positive/negative data input bit 10. l12, m12 db1[11]p/db1[11]n port 1 positive/negative data input bit 11. l13, m13 db1[12]p/db1[12]n port 1 positive/negative data input bit 12. l14, m14 db1[13]p/db1[13]n port 1 positive/negative data input bit 13. n1, p1 db0[0]p/db0[0]n port 0 posi tive/negative data input bit 0. n2, p2 db0[1]p/db0[1]n port 0 posi tive/negative data input bit 1. n3, p3 db0[2]p/db0[2]n port 0 posi tive/negative data input bit 2. n4, p4 db0[3]p/db0[3]n port 0 posi tive/negative data input bit 3. n5, p5 db0[4]p/db0[4]n port 0 posi tive/negative data input bit 4. n6, p6 db0[5]p/db0[5]n port 0 posi tive/negative data input bit 5. n7, p7 db0[6]p/db0[6]n port 0 posi tive/negative data input bit 6. n8, p8 db0[7]p/db0[7]n port 0 posi tive/negative data input bit 7. n9, p9 db0[8]p/db0[8]n port 0 posi tive/negative data input bit 8. n10, p10 db0[9]p/db0[9]n port 0 posi tive/negative data input bit 9. n11, p11 db0[10]p/db0[10]n port 0 positive/negative data input bit 10. n12, p12 db0[11]p/db0[11]n port 0 positive/negative data input bit 11. n13, p13 db0[12]p/db0[12]n port 0 positive/negative data input bit 12. n14, p14 db0[13]p/db0[13]n port 0 positive/negative data input bit 13.
ad9737a/AD9739A data sheet rev. | page 14 of 64 typical performance characteri stics ad9737a static l inearity i outfs = 20 ma, nominal supplies, t a = 25c, unless otherwise noted. 0.3 ?0.4 0 2048 error (lsb) code ?0.3 ?0.2 ?0.1 0 0.1 0.2 256 512 768 1024 1280 1536 1792 09616-109 figure 9 . typical inl, 20 ma at 25c 0.4 ?0.3 0 2048 error (lsb) code ?0.2 ?0.1 0 0.1 0.2 0.3 256 512 768 1024 1280 1536 1792 09616- 1 10 figure 10 . typical dnl, 20 ma at 25c 0.25 ?0.25 0 2048 error (lsb) code ?0.20 ?0.10 ?0.15 ?0.05 0 0.10 0.05 0.15 0.20 256 512 768 1024 1280 1536 1792 09616- 11 1 figure 11 . typical inl, 10 ma at 25c 0.25 ?0.25 0 2048 error (lsb) code ?0.20 ?0.10 ?0.15 ?0.05 0 0.10 0.05 0.15 0.20 256 512 768 1024 1280 1536 1792 09616- 1 12 figure 12 . typical dnl, 10 ma at 25c 0.6 ?0.6 ?0.5 ?0.4 ?0.3 0 2048 error (lsb) code ?0.2 ?0.1 0 0.1 0.2 0.3 0.5 0.4 256 512 768 1024 1280 1536 1792 09616- 1 13 figure 13 . typical inl, 30 ma at 25c 0.2 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 0 2048 error (lsb) code ?0.2 ?0.1 0 0.1 256 512 768 1024 1280 1536 1792 09616- 1 14 figure 14 . typical dnl, 30 ma at 25c c
data sheet ad9737a/AD9739A rev. | page 15 of 64 ac (normal mode ) i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. 10db/div stop 2.4ghz st art 20mhz vbw 20khz 09616- 1 15 figure 15 . single tone spectrum at f out = 91 mhz, f dac = 2.4 gsps 10db/div vbw 20khz stop 2.4ghz st art 20mhz 09616- 1 16 figure 16 . single - tone spectrum at f out = 1091 mhz, f dac = 2.4 gsps 90 80 0 10 20 30 40 50 60 70 0 1200 1000 800 600 400 200 sfdr (dbc) f out (mhz) 1.6gsps 2.4gsps 1.2gsps 2.0gsps 09616- 1 17 figure 17 . sfdr vs. f out over f dac 120 100 80 60 40 20 0 0 200 400 600 800 1000 1200 1400 iimd (dbc) f out (mhz) 2.0gsps 1.6gsps 1.2gsps 2.4gsps 09616- 1 18 figure 18 . imd vs. f out over f dac ?150 ?170 0 200 400 600 800 1000 1200 nsd (dbm/hz) f out (mhz) 1.2gsps 2.4gsps ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 09616- 1 19 figure 19 . single - tone nsd over f out ?150 ?170 0 200 400 600 800 1000 1200 nsd (dbm/hz) f out (mhz) 1.2gsps 2.4gsps ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 09616-120 figure 20 . eight - tone nsd o ver f out c
ad9737a/AD9739A data sheet rev. | page 16 of 64 f dac = 2 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. 90 30 0 200 300 100 400 600 700 500 900800 1000 sfdr (dbc) f out (mhz) 35 40 45 50 55 60 65 70 75 80 85 ?3dbfs 0dbfs ?6dbfs 09616-121 figure 21 . sfdr vs. f out over digital full scale 90 30 0 200 400 600 800 1000 sfdr (dbc) f out (mhz) 40 50 60 70 80 ?3dbfs 0dbfs ?6dbfs 09616-122 figure 22 . sfdr for second harmonic vs. f out over dig ital full scale 90 30 0 200 400 600 800 1000 sfdr (dbc) f out (mhz) 40 50 60 70 80 0dbfs ?6dbfs ?3dbfs 09616-123 figure 23 . sfdr for third harmonic vs. f out over digital full scale 100 40 0 1000 imd (dbc) f out (mhz) 0dbfs 45 50 55 60 65 70 75 80 85 90 95 100 200 300 400 500 600 700 800 900 ?3dbfs ?6dbfs 09616-124 figure 24 . imd vs. f out over digital full scale 30 40 35 0 1000 sfdr (dbc) f out (mhz) 45 50 55 60 65 70 75 80 85 90 100 200 300 400 500 600 700 800 900 30ma fs 10ma fs 20ma fs 09616-125 figure 25 . sfdr vs. f out over dac i ou tfs 40 0 1000 imd (dbc) f out (mhz) 45 50 55 60 65 70 75 80 85 90 95 100 100 200 300 400 500 600 700 800 900 20ma fs 30ma fs 10ma fs 09616-126 figure 26 . imd vs. f out over dac i outfs c
data sheet ad9737a/AD9739A rev. | page 17 of 64 ac (mix - mode) f dac = 2.1 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. 09616-127 30 40 35 0 1000 sfdr (dbc) f out (mhz) 45 50 55 60 65 70 75 80 85 90 100 200 300 400 500 600 700 800 900 +8 5 c ?40 c +2 5 c figure 27 . sfdr vs. f out over temperature 09616-128 40 0 1000 imd (dbc) f out (mhz) 45 50 55 60 65 70 75 80 85 90 95 100 100 200 300 400 500 600 700 800 900 ?40 c +2 5 c +8 5 c figur e 28 . imd vs. f out over temperature 09616-129 ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +2 5 c +8 5 c figure 29 . single - tone nsd vs. f out over temperature 09616-130 ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +2 5 c +8 5 c figure 30 . eigh t- tone nsd vs. f out over temperature sp an 54.68mhz sweep 1.509s center 350mhz #res bw 30khz upper fi l ter on on on on on dbc ?79.73 ?80.21 ?80.85 ?81.41 ?81.46 dbc ?80.51 ?81. 11 ?81.67 ?81.61 ?82.19 dbm ?92.90 ?93.38 ?94.01 ?94.58 ?94.63 lower dbm ?93.67 ?94.27 ?94.84 ?94.77 ?95.35 integ bw 3.840mhz 3.840mhz 3.840mhz 3.840mhz 3.840mhz offset freq 5.000mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz carrier power ?13.167dbm/3.84mhz acp-ibw 10db/div ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 09616-131 vbw 3khz ?81.4dbc ?81.1dbc ?80.5dbc ?13.2dbm ?80.8dbc ?80.2dbc ?79.7dbc ?81.5dbc ?81.6dbc ?82.2dbc ?81.7dbc figure 31 . single - carrier wcdma at 350 mhz, f dac = 2457.6 msps ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 200 400 600 800 1400 1200 1000 aclr (dbc) f out (mhz) 09616-226 first adj ch fifth adj ch second adj ch figure 32 . single - carrier wcdma aclr vs. f out at 2457.6 msps c
ad9737a/AD9739A data sheet rev. | page 18 of 64 f dac = 2.1 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. 09616-132 10db/div stop 2.4ghz sweep 7.174s (601pts) st art 20mhz #res bw 20khz vbw 20khz figure 33 . single - tone spectrum at f ou t = 2.31 ghz, f dac = 2.4 gsps 09616-133 10db/div stop 2.4ghz sweep 7.174s (601pts) st art 20mhz #res bw 20khz vbw 20khz figure 34 . single - tone spectrum at f out = 1.31 ghz, f dac = 2.4 gsps 09616-134 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f out (mhz) sfdr (dbc) figure 35 . sfdr in mix - mode vs. f out at 2.4 gsps 09616-135 30 40 50 60 70 90 80 100 1000 1300 1200 1100 1400 1500 1600 1700 1800 1900 2000 imd (dbc) f out (mhz) figure 36 . imd in mix - mode vs. f out at 2.4 gsps 09616-136 sp an 54.68mhz sweep 1.509s center 2.108mhz #res bw 30khz upper fi l ter on on on on on dbc ?69.84 ?71.15 ?71.75 ?72.19 ?72.70 dbc ?69.82 ?69.93 ?71.77 ?72.26 ?71.90 dbm ?89.36 ?90.67 ?91.28 ?91.71 ?92.22 lower dbm ?88.34 ?89.46 ?91.29 ?91.79 ?91.42 integ bw 3.840mhz 3.840mhz 3.840mhz 3.840mhz 3.840mhz offset freq 5.000mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz carrier power ?19.526dbm/3.84mhz acp-ibw 10db/div ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 vbw 3khz ?72.7dbc ?71.8dbc ?69.9dbc ?68.8dbc ?19.5dbm ?72.3dbc ?71.9dbc ?69.8dbc ?71.1dbc ?71.8dbc ?72.2dbc figure 37 . typical single - carrier wcdma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 1307.6 3557.6 1557.6 1807.6 2057.6 2307.6 2557.6 2807.6 3057.6 3307. 6 second nyquist zone third nyquist zone first adj ch third adj ch ac lr (db c) 09616-137 f out (mhz) second adj ch figure 38 . s ingle - carrier wcdma aclr vs. f out , f dac = 2457.6 msps c
data sheet ad9737a/AD9739A rev. | page 19 of 64 f dac = 2.1 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. 09616-138 sp an 54.68mhz sweep 1.509s center 2.808mhz #res bw 30khz upper fi l ter on on on on on dbc ?65.56 ?65.82 ?65.98 ?66.06 ?66.14 dbc ?65.65 ?65.70 ?65.81 ?65.84 ?65.84 dbm ?94.72 ?94.98 ?95.14 ?95.22 ?95.31 lower dbm ?94.81 ?94.86 ?94.97 ?95.00 ?95.00 integ bw 3.840mhz 3.840mhz 3.840mhz 3.840mhz 3.840mhz offset freq 5.000mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz carrier power ?26.161dbm/3.84mhz acp-ibw 10db/div ?45 ?55 ?65 ?75 ?85 ?95 ?115 ?105 ?125 vbw 3khz ?66.1dbc ?66.1dbc ?65.8dbc ?65.7dbc ?65.6dbc ?29.2dbm ?65.8dbc ?65.8dbc ?65.6dbc ?65.8dbc ?66.0dbc figure 39 . typical single - carrier wcdma aclr performance at 2.8 ghz, f dac = 2457.6 msps (third nyquist zone) 09616-139 sp an 69.68mhz sweep 1.922s center 2.108mhz #res bw 30khz upper fi l ter on on on on on dbc ?64.93 ?64.26 ?65.21 ?65.74 ?66.13 dbc ?65.42 ?64.93 ?65.12 ?65.24 ?65.61 dbm ?92.23 ?91.56 ?92.50 ?93.04 ?93.42 lower dbm ?92.72 ?92.23 ?92.42 ?92.53 ?92.91 integ bw 3.840mhz 3.840mhz 3.840mhz 3.840mhz 3.840mhz offset freq 5.000mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz carrier power ?21.446dbm/15.36mhz acp-ibw 10db/div ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 ?130 vbw 3khz ?65.2dbc ?65.4dbc ?27.6dbm ?27.6dbm ?27.3dbm ?27.4dbm ?64.9dbc ?64.9dbc ?64.3dbc ?65.7dbc ?66.1dbc ?65.1dbc ?65.2dbc ?65.6dbc figure 40 . typical four - carrier wcdma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) 09616-140 sp an 69.68mhz sweep 1.922s center 2.808mhz #res bw 30khz upper fi l ter on on on on on dbc ?58.20 ?58.15 ?58.26 ?58.33 ?58.21 dbc ?58.05 ?57.95 ?57.95 ?57.97 ?58.05 dbm ?95.26 ?95.21 ?95.32 ?95.39 ?95.27 lower dbm ?95. 11 ?95.02 ?95.01 ?95.04 ?95. 11 integ bw 3.840mhz 3.840mhz 3.840mhz 3.840mhz 3.840mhz offset freq 5.000mhz 10.00mhz 15.00mhz 20.00mhz 25.00mhz carrier power ?31.097dbm/15.36mhz acp-ibw 10db/div ?60 ?70 ?80 ?90 ?100 ?110 ?130 ?120 ?140 vbw 3khz ?58.3dbc ?58.0dbc ?37.4dbm ?37.1dbm ?37.1dbm ?36.9dbm ?58.2dbc ?58.0dbc ?58.1dbc ?58.3dbc ?58.2dbc ?57.9dbc ?58.0dbc ?58.0dbc figure 41 . typical four - carrier wcdma aclr performance at 2.8 g hz, f dac = 2457.6 msps (third nyquist zone) c
ad9737a/AD9739A data sheet rev. | page 20 of 64 one - carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-141 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?10.238dbm ?74.467db ?77.224db ?78.437db ?67.413db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?10.238dbm ?74.467db ?77.224db ?78.437db ?67.413db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 200.10mhz 199.50mhz 399.95mhz 599.45mhz 413.25mhz ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 41 1 21 31 51 figure 42 . low band wideband acl r 09616-142 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?1 1.538dbm ?74.399db ?74.344db ?68.472db ?66.197db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?1 1.538dbm ?74.421db ?76.294db ?68.472db ?66.156db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 550.65mhz ?487.35mhz 125.40mhz 253.65mhz 62.70mhz ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 31 21 1 41 51 figure 43 . mid band wideband aclr 09616-143 10db/div vbw 2khz stop 1ghz sweep 24. 1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?14.446dbm ?60.856db ?66.013db ?68.697db ?63.533db ?68.162db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?14.418dbm ?60.856db ?66.000db ?68.751db ?63.533db ?66.162db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 948.70mhz ?393.30mhz ?553.85mhz ?612.75mhz ?335.35mhz ?57.95mhz ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 31 51 41 21 61 1 figure 44 . high band wideband aclr 09616-144 sp an 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper fi l ter off off off off off dbc ?57.47 ?79.87 ?78.96 ?78.69 ?78.68 dbc ?58.34 ?79.27 ?78.44 ?78.59 ?78.41 dbm ?67.70 ?90.10 ?89.19 ?88.92 ?88.90 lower dbm ?68.57 ?89.50 ?88.66 ?88.82 ?88.63 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?10.226dbm/6mhz acp-ibw 10db/div ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?78.4dbc ?78.6dbc ?78.4dbc ?79.3dbc ?10.2dbm ?79.9dbc ?79.0dbc ?78.7dbc ?78.7dbc figure 45 . low band narrow - band aclr 09616-145 sp an 54mhz sweep 1.49s vbw 3khz center 550mhz #res bw 30khz upper fi l ter off off off off off dbc ?60.92 ?74.14 ?74.68 ?74.91 ?75.34 dbc ?59.37 ?74.02 ?74.53 ?75.00 ?75.97 dbm ?73.03 ?86.25 ?86.79 ?87.01 ?87.44 lower dbm ?71.48 ?86.12 ?86.63 ?87. 11 ?88.08 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?12.104dbm/6mhz acp-ibw 10db/div ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?76.0dbc ?75.0dbc ?74.5dbc ?74.0dbc ?12.1dbm ?74.1dbc ?74.7dbc ?75.3dbc ?78.9dbc figure 46 . mid band narrow - band aclr 09616-146 sp an 54mhz sweep 1.49s vbw 3khz center 950mhz #res bw 30khz upper fi l ter off off off off off dbc ?61.30 ?69.39 ?70.50 ?71.02 ?71.75 dbc ?57.84 ?69.02 ?70.01 ?70.89 ?71.94 dbm ?74.89 ?82.98 ?84.09 ?84.61 ?85.34 lower dbm ?71.43 ?82.61 ?83.60 ?84.48 ?85.53 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?13.589dbm/6mhz acp-ibw 10db/div ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?71.9dbc ?70.9dbc ?70.0dbc ?69.0dbc ?13.6dbm ?69.4dbc ?70.5dbc ?71.7dbc ?71.0dbc figure 47 . high band narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 21 of 64 four - carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 09616-147 vbw 2khz 1 21 51 31 41 function v alue function width function ?18.419dbm ?69.277db ?71.485db ?72.343db ?59.518db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?18.419dbm ?69.252db ?71.282db ?72.100db ?59.520db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 200.10mhz 221.35mhz 431.30mhz 651.70mhz 413.25mhz figure 48 . low ba nd wideband aclr stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 09616-148 vbw 2khz 1 21 51 31 41 function v alue function width function ?19.885dbm ?70.252db ?69.581db ?67.793db ?58.085db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?19.885dbm ?70.252db ?69.535db ?67.793db ?58.085db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 549.70mhz ?486.40mhz 126.35mhz 228.00mhz 63.65mhz figure 49 . mid band wideband aclr stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-149 vbw 2khz 1 21 51 61 31 41 function v alue function width function ?21.676dbm ?62.206db ?65.730db ?67.064db ?56.405db ?65.729db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?21.631dbm ?62.206db ?65.730db ?67.064db ?56.405db ?65.729db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 950.60mhz ?415.15mhz ?529.15mhz ?610.85mhz ?337.25mhz ?59.85mhz figure 50 . high band wideband aclr sp an 54mhz sweep 1.49s center 218mhz #res bw 30khz upper fi l ter off off off off off dbc ?58.82 ?73.28 ?72.92 ?73.50 ?73.74 dbc ?10.82 ?0.566 ?0.123 ?0.028 ?53.18 dbm ?76.71 ?91.17 ?90.81 ?91.39 ?91.63 lower dbm ?28.71 ?18.46 ?17.77 ?17.86 ?71.07 integ bw 750khz 5.25khz 6mhz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?17.892dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-150 vbw 3khz ?53.2dbc 0dbc ?73.5dbc ?72.9dbc ?73.7dbc 0.1dbc ?0.6dbc ?17.9dbc ?73.3dbc figure 51 . low band narrow - band aclr (worse side) sp an 54mhz sweep 1.49s center 550mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.49 ?0.526 ?0.160 ?0.024 ?54.18 dbc ?58.29 ?68.28 ?68.47 ?69.72 ?70.64 dbm ?30.02 ?20.06 ?19.69 ?19.56 ?73.72 lower dbm ?77.82 ?87.81 ?88.00 ?89.25 ?90.17 integ bw 750khz 5.25khz 6mhz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?17.892dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-151 vbw 3khz ?70.6dbc ?69.7dbc 0dbc ?0.2dbc ?54.2dbc ?68.5dbc ?68.3dbc ?19.5dbc ?0.5dbc figure 52 . mid band narrow - band aclr (worse side) sp an 54mhz sweep 1.49s center 950mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.04 ?0.437 ?0.172 ?0.098 ?53. 11 dbc ?59.52 ?63.90 ?64.29 ?65.41 ?66.57 dbm ?32.55 ?21.95 ?21.68 ?21.41 ?74.62 lower dbm ?81.03 ?85.41 ?85.80 ?86.92 ?88.08 integ bw 750khz 5.25khz 6mhz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?21.510dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-152 vbw 3khz ?66.6dbc ?65.4dbc 0.1dbc ?0.2dbc ?53.1dbc ?64.3dbc ?63.9dbc ?21.5dbm ?0.4dbc figure 53 . high band narrow - band aclr (worse side) c
ad9737a/AD9739A data sheet rev. | page 22 of 64 eight - carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwis e noted. stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 09616-153 vbw 2khz 1 21 31 function v alue function width function ?22.253dbm ?66.457db ?55.791db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?22.253dbm ?66.457db ?55.791db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 200.10mhz 235.60mhz 431.25mhz figure 54 . low band wideband aclr stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-154 vbw 2khz 1 21 31 function v alue function width function ?23.585dbm ?54.206db ?66.628db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?23.586dbm ?54.209db ?66.696db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 550.65mhz 62.70mhz 167.20mhz figure 55 . mid band wideband aclr stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 09616-155 vbw 2khz 1 21 51 41 31 function v alue function width function ?26.330dbm ?61.574db ?63.268db ?62.616db ?51.728db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?26.330dbm ?61.549db ?63.183db ?62.616db ?51.728db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 950.60mhz ?448.40mhz ?582.35mhz ?80.75mhz ?338.20mhz figure 56 . high band wideband aclr 09616-156 sp an 42mhz sweep 1.159s center 200mhz #res bw 30khz upper fi l ter off off off off dbc ?10.96 ?0.572 ?0.250 ?0.186 dbc ?55.24 ?70.28 ?69.23 ?69. 11 dbm ?34.25 ?23.86 ?23.54 ?23.47 lower dbm ?78.53 ?93.56 ?92.52 ?92.40 integ bw 750khz 5.25mhz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz carrier power ?23.288dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 vbw 3khz ?69.1dbc ?69.2dbc ?70.3dbc ?23.3dbc ?0.6dbc ?0.2dbc ?0.3dbc figure 57 . low band narrow -b and aclr (worse side) 09616-157 sp an 42mhz sweep 1.159s center 592mhz #res bw 30khz upper fi l ter off off off off dbc ?56.23 ?66.75 ?66.45 ?66.78 dbc ?10.79 ?0.089 ?0.289 ?0.145 dbm ?79.91 ?90.43 ?90.12 ?90.46 lower dbm ?34.47 ?23.76 ?23.39 ?23.53 integ bw 750khz 5.25khz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz carrier power ?23.676dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 vbw 3khz 0.1dbc 0.3dbc ?66.8dbc ?66.4dbc ?0.1dbc ?23.7dbc ?66.8dbc figure 58 . mid band narrow - band aclr (worse side) 09616-158 sp an 54mhz sweep 1.49s center 950mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.99 ?0.366 ?0.073 ?0.053 ?0.225 dbc ?60.71 ?62.67 ?62.21 ?62.68 ?63.49 dbm ?37.38 ?26.75 ?26.31 ?26.33 ?26.16 lower dbm ?87.10 ?89.06 ?88.60 ?89.07 ?89.88 integ bw 750khz 5.25khz 6mhz 6mhz 6mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?26.388dbm/6mhz acp-ibw 10db/div ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 vbw 3khz ?63.5dbc ?62.7dbc 0.1dbc 0.1dbc 0.2dbc ?62.2dbc ?62.7dbc ?26.4dbm ?0.4dbc figure 59 . high band narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 23 of 64 16- carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nomi nal supplies, t a = 25c , unless otherwise noted. 09616-159 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?26.391dbm ?64.927db ?65.369db ?51.688db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?26.390dbm ?64.8 1 1db ?65.150db ?51.688db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 160.20mhz 80.75mhz 232.75mhz 452.20mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 1 21 31 41 figure 60 . low band wideband aclr 09616-160 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?27.503dbm ?63.639db ?62.631db ?63.408db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?27.503dbm ?63.639db ?62.748db ?63.408db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 549.70mhz ?486.40mhz 126.35mhz 254.60mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 21 1 31 41 figure 61 . mid band wideband aclr 09616-161 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?28.493dbm ?60.066db ?61.070db ?61.014db ?49.417db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?28.493dbm ?60.066db ?61.070db ?61.014db ?49.417db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 899.30mhz ?343.90mhz ?504.45mhz ?563.35mhz ?285.95mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 41 31 51 21 1 figure 62 . high band wideband aclr 09616-162 sp an 54mhz sweep 1.49s vbw 3khz center 160mhz #res bw 30khz upper fi l ter off off off off off dbc ?61.30 ?65.24 ?63.93 ?64.07 ?64.08 dbm ?87.55 ?91.49 ?90.18 ?90.32 ?90.33 lower dbc ?10.95 ?0.314 ?0.166 ?0.125 ?0.034 dbm ?37.20 ?26.56 ?26.42 ?26.38 ?26.28 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?25.250dbm/6mhz acp-ibw 10db/div 0.0dbc ?0.1dbc ?0.2dbc ?0.3dbc ?26.3dbm ?65.2dbc ?63.9dbc ?64.1dbc ?64.1dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 63 . low band narrow - band aclr 09616-163 sp an 54mhz sweep 1.49s vbw 3khz center 640mhz #res bw 30khz upper fi l ter off off off off off dbc ?60.24 ?63.87 ?62.76 ?63.08 ?63.33 dbm ?87.62 ?91.26 ?90.15 ?90.46 ?90.72 lower dbc ?1 1.65 ?0.239 ?0.199 ?0.282 ?0.288 dbm ?39.04 ?27.63 ?27.19 ?27.10 ?27.10 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?27.386dbm/6mhz acp-ibw 10db/div 0.3dbc 0.3dbc 0.2dbc ?0.2dbc ?27.4dbm ?63.9dbc ?62.8dbc ?63.3dbc ?63.1dbc ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 ?125 figure 64 . mid band narrow - band aclr (worse side) 09616-164 sp an 54mhz sweep 1.49s vbw 3khz center 900mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.14 ?0.446 ?0.271 ?0.318 ?0.147 dbm ?39.25 ?28.56 ?28.38 ?28.43 ?28.26 lower dbc ?58.27 ?61.84 ?61.30 ?62. 11 ?62.66 dbm ?86.38 ?89.95 ?89.42 ?90.22 ?90.77 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?28. 1 12dbm/6mhz acp-ibw 10db/div ?62.7dbc ?62.1dbc ?61.3dbc 61.8dbc ?28.1dbm ??0.4dbc ?0.3dbc ?0.1dbc ?0.3dbc ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 ?125 figure 65 . high band narrow - band aclr c
ad9737a/AD9739A data sheet rev. | page 24 of 64 32- carrier docsis perfo rmance (normal mode) i outfs = 20 ma , f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-165 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?29.853dbm ?61.410db ?61.639db ?48.122db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?29.852dbm ?61.581db ?61.313db ?48.122db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 256.15mhz 94.05mhz 243.20mhz 356.25mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 1 31 21 41 figure 66 . low band wideband aclr 09616-166 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?29.461dbm ?61.621db ?61.831db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?29.461dbm ?61.621db ?61.831db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 550mhz ?462.65mhz 314.45mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 21 1 31 figure 67 . mid band wideband aclr 09616-167 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?32.396dbm ?57.463db ?58.079db ?45.705db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?32.396dbm ?57.463db ?58.079db ?45.705db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 799.55mhz ?138.70mhz ?601.35mhz ?187.15mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 21 1 41 31 figure 68 . high band wideb and aclr 09616-168 sp an 54mhz sweep 1.49s vbw 3khz center 256mhz #res bw 30khz upper fi l ter off off off off off dbc ?60.27 ?65.64 ?64.12 ?64.24 ?64.12 dbm ?88.50 ?93.87 ?92.35 ?92.47 ?92.35 lower dbc ?10.80 ?0.336 0.060 0.081 0.080 dbm ?39.03 ?28.56 ?28.17 ?28.15 ?28.15 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?28.229dbm/6mhz acp-ibw 10db/div 0.1dbc 0.1dbc 0.1dbc ?0.3dbc ?28.2dbm ?65.6dbc ?64.1dbc ?64.1dbc ?64.2dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 69 . low band narrow - band aclr 09616-169 sp an 54mhz sweep 1.49s vbw 3khz center 550mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.88 ?0.576 ?0.222 ?0.423 ?0.133 dbm ?40.39 ?30.09 ?29.73 ?29.93 ?29.63 lower dbc ?58.70 ?62.34 ?61.36 ?61.70 ?61.84 dbm ?88.21 ?91.85 ?90.87 ?91.21 ?91.36 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?29.512dbm/6mhz acp-ibw 10db/div ?61.8dbc ?61.7dbc ?61.4dbc ?62.3dbc ?29.5dbm ??0.6dbc ?0.2dbc ?0.1dbc ?0.4dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 70 . mid band narrow - band aclr (worse side) 09616-170 sp an 54mhz sweep 1.49s vbw 3khz center 800mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.73 ?0.201 0.300 0.296 0.230 dbm ?42.89 ?32.35 ?31.85 ?31.86 ?31.92 lower dbc ?59.39 ?61.40 ?59.86 ?59.61 ?60.04 dbm ?91.54 ?93.55 ?92.01 ?91.77 ?92.20 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?32.154dbm/6mhz acp-ibw 10db/div ?60.0dbc ?59.6dbc ?59.9dbc ?61.4dbc ?32.2dbm ??0.2dbc 0.3dbc 0.2dbc 0.3dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 71 . high band narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 25 of 64 64- and 128- carrier docsis per formance (normal mod e) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-171 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?33.680dbm ?46.450db ?56.577db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?33.679dbm ?46.452db ?56.577db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 448.05mhz 165.30mhz 372.40mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 21 31 1 figure 72 . low band wideb and aclr 09616-172 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?34.413dbm ?56.033db ?36.289dbm 6mhz 6mhz 6mhz band power band power band power () () () y ?34.413dbm ?56.033db ?36.289dbm f f f 1 1 1 1 2 3 x n 1 n mode mkr sc l trc 599.10mhz ?292.60mhz 978.15mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 1 21 3 figure 73 . high band wideband aclr 09616-173 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?35.909dbm ?53.920db ?38.646dbm 6mhz 6mhz 6mhz band power band power band power () () () y ?34.909dbm ?53.920db ?38.646dbm f f f 1 1 1 1 2 3 x n 1 n mode mkr sc l trc 69.95mhz 855.00mhz 831.85mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 1 21 3 figure 74 . 128 - carrier low band wideband aclr 09616-174 sp an 54mhz sweep 1.49s vbw 3khz center 448mhz #res bw 30khz upper fi l ter off off off off off dbc ?59.56 ?60.04 ?58.69 ?59.04 ?58.86 dbm ?92.93 ?93.41 ?92.06 ?92.40 ?92.23 lower dbc ?1 1.02 ?0.337 0.050 0.064 0.099 dbm ?44.39 ?33.74 ?33.32 ?33.30 ?33.27 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?33.368dbm/6mhz acp-ibw 10db/div 0.1dbc 0.1dbc 0.0dbc ?0.4dbc ?33.4dbm ?60.0dbc ?58.7dbc ?58.9dbc ?59.0dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 75 . 64 - carrier low band narrow - band aclr 09616-175 sp an 54mhz sweep 1.49s vbw 3khz center 600mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.06 ?0.380 ?0.004 ?0.012 0.043 dbm ?44.91 ?34.23 ?33.85 ?33.86 ?33.81 lower dbc ?58.63 ?59.29 ?58.37 ?57.84 ?58.04 dbm ?92.48 ?93.14 ?92.22 ?91.69 ?91.89 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?33.849dbm/6mhz acp-ibw 10db/div ?58.0dbc ?57.8dbc ?58.4dbc ?59.3dbc ?33.8dbm ??0.4dbc 0.0dbc 0.0dbc 0.0dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 76 . 64 - carrier high band narrow - band aclr 09616-218 sp an 54mhz sweep 1.49s vbw 3khz center 832mhz #res bw 30khz upper fi l ter off off off off off dbc ?59.28 ?54.33 ?53.36 ?53.35 ?53.07 dbm ?97.73 ?92.79 ?91.82 ?91.81 ?91.53 lower dbc ?1 1.07 ?0.210 0.353 0.253 0.292 dbm ?49.53 ?38.67 ?38.10 ?38.20 ?38.16 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?38.456dbm/6mhz acp-ibw 10db/div 0.3dbc 0.3dbc 0.4dbc ?0.2dbc ?38.5dbm ?54.3dbc ?53.4dbc ?53.1dbc ?53.3dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 77 . 12 8 - carrier narrow - band aclr c
ad9737a/AD9739A data sheet rev. | page 26 of 64 typical performance characteristics AD9739A static linearity ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 code error (lsb) 2048 0 4096 6144 8192 10,240 12,288 14,336 16,384 09616-207 figure 78 . typical inl, 20 ma at 25c ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-210 figure 79 . typical dnl , 20 ma at 25c 0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-208 figure 80 . typical inl, 20 ma at ?40c ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-2 11 figure 81 . typical dnl, 20 ma at ?40c ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-209 figure 82 . typical inl, 20 ma at 85c ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-212 figure 83 . typical dnl, 20 ma at 85c c
data sheet ad9737a/AD9739A rev. | page 27 of 64 code error (lsb) 2048 0 4096 6144 8192 10,240 12,288 14,336 16,384 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 09616-213 figure 84 . typical inl, 10 ma at 25c ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-216 figure 85 . typical dnl, 10 ma at 25c 0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-214 figure 86 . typical inl, 30 ma at 25c ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 code error (lsb) 2048 4096 6144 8192 10,240 12,288 14,336 16,384 09616-217 figure 87 . typical dnl, 30 ma at 25c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 total dvdd18 clkvdd avdd dvdd33 f dac (mhz) power (w) 09616-215 figu re 88 . power consumption vs. f dac at 25c c
ad9737a/AD9739A data sheet rev. | page 28 of 64 ac (normal mode) i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. vbw 10khz 10db/div stop 2.4ghz st art 20mhz 09616-007 figure 89 . single - tone spectrum at f out = 91 mhz, f dac = 2.4 gsps f out (mhz) sfdr (dbc) 30 35 40 45 50 55 60 65 70 75 80 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1.6gsps 1.2gsps 2.4gsps 2.0gsps 09616-008 figure 90 . sfdr vs. f out over f dac nsd (dbm/hz) ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 1.2gsps 2.4gsps f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 09616-009 figure 91 . single - tone nsd vs. f out vbw 10khz 10db/div stop 2.4ghz st art 20mhz 09616-010 figure 92 . single - tone spectrum at f out = 1091 mhz, f dac = 2.4 gsps f out (mhz) imd (dbc) 30 0 100 200 300 400 500 600 700 800 900 1000 35 40 45 50 55 60 65 70 75 80 85 90 95 100 1100 1200 1.2gsps 1.6gsps 2.0gsps 2.4gsps 09616-0 11 figure 93 . imd vs. f out over f dac f out (mhz) nsd (dbm/hz) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 ?170 ?169 ?168 ?167 ?166 ?165 ?164 ?163 ?162 ?161 ?160 2.4gsps 1.2gsps 09616-012 figure 94 . eight - tone nsd vs. f out c
data sheet ad9737a/AD9739A rev. | page 29 of 64 f dac = 2 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. ?3dbfs 0dbfs f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 ?6dbfs 09616-013 figure 95 . sfdr vs. f out over digital full sca le f out (mhz) sf dr (db) 30 0 100 200 300 400 500 600 700 800 900 1000 40 50 60 70 80 90 0dbfs ?3dbfs ?6dbfs 09616-014 figure 96 . sfdr for second harmonic over f out vs. digital full scale f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 10ma fs 20ma fs 30ma fs 09616-015 figure 97 . sfdr vs. f out over dac i outfs f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 0dbfs ?6dbfs ?3dbfs 09616-016 figure 98 . imd vs. f out over digital full scale f out (mhz) sf dr (db) 30 0 100 200 300 400 500 600 700 800 900 1000 40 50 60 70 80 90 ?6dbfs ?3dbfs 0dbfs 09616-017 figu re 99 . sfdr for third harmonic over f out vs. digital full scale f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 10ma fs 20ma fs 30ma fs 09616-018 figure 100 . imd vs. f out over dac i outfs c
ad9737a/AD9739A data sheet rev. | page 30 of 64 f dac = 2 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 +2 5 c +8 5 c ?40 c 09616-019 figure 101 . sfdr vs. f out over temperature ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +2 5 c ?40 c +8 5 c 09616-020 figure 102 . single - tone nsd vs. f out over temperature vbw 300khz 10db/div sp an 53.84mhz sweep 174.6ms (601pts) center 350.27mhz #res bw 30khz rms resu l ts carrier power ?14.54dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?79.90 ?80.60 ?80.90 ?80.62 ?80.76 (dbm) ?94.44 ?95.14 ?95.45 ?95.16 ?95.30 lower (dbc) ?79.03 ?79.36 ?80.73 ?80.97 ?80.95 (dbm) ?93.57 ?94.40 ?95.27 ?95.51 ?95.49 upper 09616-021 figure 103 . single - carrier wcdma at 350 mhz, f dac = 2457.6 msps f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 +2 5 c ?40 c +8 5 c 09616-022 figure 104 . imd vs. f out over temperature ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ?150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +2 5 c ?40 c +8 5 c 09616-023 figure 105 . eight - tone nsd vs. f out over temperature ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 0 200 400 600 800 1400 1200 1000 aclr (dbc) f out (mhz) 09616-225 first adj ch fifth adj ch second adj ch figure 106 . single - carrier wcdma aclr vs. f out at 2457.6 msps c
data sheet ad9737a/AD9739A rev. | page 31 of 64 ac ( mix - mode ) f dac = 2.4 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. vbw 10khz 10db/div stop 2.4ghz sweep 28.7s (601pts) st art 20mhz #res bw 10khz 09616-026 figure 107 . single - tone spectrum at f out = 2.31 ghz, f dac = 2.4 gsps 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f out (mhz) sfdr (dbc) 09616-027 figure 108 . sfdr in mix - mode vs. f out at 2.4 gsps vbw 300khz 10db/div sp an 53.84mhz sweep 174.6ms (601pts) center 2.10706mhz #res vw 30khz rms resu l ts carrier power ?21.43dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?68.99 ?72.09 ?72.86 ?74.34 ?74.77 (dbm) ?90.43 ?93.52 ?94.30 ?95.77 ?96.20 lower (dbc) ?63.94 ?71.07 ?71.34 ?72.60 ?73.26 (dbm) ?90.37 ?92.50 ?92.77 ?94.03 ?94.70 upper 09616-032 fi gure 109 . typical single - carrier wcdma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) vbw 10khz 10db/div stop 2.4ghz st art 20mhz stop 2.4ghz sweep 28.7s (601pts) st art 20mhz #res bw 10khz 09616-030 figure 110 . single - tone spectrum in mix - mode at f out = 1.31 ghz, f dac = 2.4 gsps 30 35 40 45 50 55 60 65 70 75 80 85 90 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f out (mhz) imd (dbc) 09616-031 figure 111 . imd in mix - mode vs. f out at 2.4 gsps ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 second nyquist zone third nyquist zone first adj ch second adj ch fifth adj ch f out (mhz) ac lr (db c) 09616-025 figure 112 . single - carrier wcdma aclr vs. f out at 2457.6 msps c
ad9737a/AD9739A data sheet rev. | page 32 of 64 f dac = 2.4 gsps, i outfs = 20 ma, nominal supplies, t a = 25c , unless otherwise noted. vbw 300khz 10db/div sp an 53.84mhz sweep 174.6ms (601pts) center 2.807ghz #res bw 30khz rms resu l ts carrier power ?24.4dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?64.90 ?66.27 ?68.44 ?70.20 ?70.85 (dbm) ?89.30 ?90.67 ?92.84 ?94.60 ?95.25 lower (dbc) ?63.82 ?65.70 ?66.55 ?68.95 ?70.45 (dbm) ?88.22 ?90.10 ?90.95 ?93.35 ?94.85 upper 09616-033 figur e 113 . typical single - carrier wcdma aclr performance at 2.8 ghz, f dac = 2457.6 msps (third nyquist zone) vbw 300khz 10db/div sp an 63.84mhz sweep 207ms (601pts) center 2.09758ghz #res bw 30khz rms resu l ts carrier power ?25.53dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 30 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 3.84 (dbc) 0.22 ?66.68 ?68.01 ?68.61 ?68.87 ?69.21 (dbm) ?25.31 ?92.21 ?93.53 ?94.14 ?94.40 ?94.74 lower (dbc) 0.24 0.14 ?66.82 ?67.83 ?67.64 ?68.50 (dbm) ?25.29 ?25.38 ?92.35 ?93.36 ?93.17 ?94.03 upper 09616-034 figure 114 . typical four - carrier wcdma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) vbw 300khz 10db/div sp an 63.84mhz sweep 207ms (601pts) center 2.81271ghz #res bw 30khz rms resu l ts carrier power ?27.98dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 30 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 3.84 (dbc) ?0.42 ?64.32 ?66.03 ?66.27 ?66.82 ?67.16 (dbm) ?28.40 ?92.30 ?94.01 ?94.24 ?94.79 ?95.13 lower (dbc) ?0.10 ?0.08 ?65.37 ?66.06 ?63.36 ?66.54 (dbm) ?28.07 ?28.06 ?93.34 ?94.03 ?93.34 ?94.51 upper 09616-035 figure 115 . typical four - carrier wcdma aclr performance at 2.8 ghz, f dac = 2457.6 msps (third nyquist zone) c
data sheet ad9737a/AD9739A rev. | page 33 of 64 one - carrier docsis perfo rmance (normal mode) f outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-176 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?1 1.475dbm ?77.042db ?76.238db ?74.526db ?75.919db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?1 1.476dbm ?77.042db ?76.238db ?74.526db ?75.919db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 200.00mhz 199.60mhz 400.05mhz 597.65mhz 413.35mhz ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 31 51 21 41 1 figure 116 . low band wideband aclr 09616-177 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?10.231dbm ?76.425db ?75.626db ?70.658db ?75.824db ?78. 1 18db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?10.231dbm ?76.444db ?75.649db ?70.658db ?75.836db ?78.054db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 549.60mhz ?485.35mhz 127.40mhz 254.70mhz 63.75mhz 293.65mhz ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 31 51 21 41 1 61 figure 117 . mid band wideband aclr 09616-178 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?13.658dbm ?66.548db ?66.990db ?69.049db ?72.789db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?13.703dbm ?65.548db ?66.990db ?69.044db ?72.789db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 979.00mhz ?484.40mhz ?1 18.65mhz ?613.60mhz ?365.65mhz ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 31 51 21 41 1 figure 118 . high band wideband aclr 09616-179 sp an 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper fi l ter off off off off off dbc ?60.16 ?81.26 ?80.72 ?80.76 ?80.78 dbm ?70.35 ?91.45 ?90.91 ?90.95 ?90.97 lower dbc ?59.38 ?81.23 ?80.71 ?80.72 ?80.73 dbm ?69.57 ?91.42 ?90.90 ?90.91 ?90.92 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?10.190dbm/6mhz acp-ibw 10db/div ?80.7dbc ?80.7dbc ?80.7dbc ?81.2dbc ?10.2dbm ?81.3bc ?80.7dbc ?80.8dbc ?80.7dbc ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 figure 119 . low band narrow - band aclr 09616-180 sp an 54mhz sweep 1.49s vbw 3khz center 550mhz #res bw 30khz upper fi l ter off off off off off dbc ?58.53 ?74.41 ?75.55 ?76.69 ?77.67 dbm ?68.90 ?84.78 ?85.92 ?87.06 ?88.03 lower dbc ?57.91 ?75.09 ?76.29 ?77.63 ?78.51 dbm ?68.28 ?85.46 ?86.65 ?88.00 ?88.88 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?10.368dbm/6mhz acp-ibw 10db/div ?78.5dbc ?77.6dbc ?76.3dbc ?75.1bc ?10.4dbm ?74.4bc ?75.6dbc ?77.7dbc ?76.7dbc ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 figure 120 . mid band narrow - band aclr 09616-181 sp an 54mhz sweep 1.49s vbw 3khz center 980mhz #res bw 30khz upper fi l ter off off off off off dbc ?61.44 ?72.10 ?73.42 ?75.03 ?76.31 dbm ?75.24 ?85.90 ?87.22 ?88.83 ?90. 11 lower dbc ?57.81 ?72.17 ?75.28 ?75.91 ?76.71 dbm ?71.61 ?85.97 ?89.08 ?89.71 ?90.50 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?13.798dbm/6mhz acp-ibw 10db/div ?76.7dbc ?75.9dbc ?75.3dbc ?72.2bc ?13.8dbm ?72.1bc ?73.4dbc ?76.3dbc ?75.0dbc ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 figure 121 . high band narrow - band aclr c
ad9737a/AD9739A data sheet rev. | page 34 of 64 four - carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps , nominal supplies, t a = 25c , unless otherwise noted. 09616-183 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?18.594dbm ?73.170db ?73.621db ?71.289db ?68.946db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?18.593dbm ?73.198db ?73.654db ?71.306db ?68.955db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 200mhz 216.60mhz 400mhz 621.30mhz 413.25mhz ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 41 1 31 21 51 figure 122 . low band wideband aclr 09616-184 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?18.760dbm ?69.536db ?71.601db ?72.833db ?75.320db ?71.997db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?18.760dbm ?69.536db ?71.601db ?72.824db ?75.786db ?71.997db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 667.80mhz ?192.20mhz ?98.15mhz ?614.00mhz ?567.45mhz ?55.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 21 41 51 61 31 1 figure 123 . mid band wideband aclr 09616-185 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?21.029dbm ?60.683db ?69.390db ?71.847db ?66.954db ?68.889db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?20.040dbm ?60.683db ?69.390db ?71.954db ?66.954db ?68.889db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 987.95mhz ?490.50mhz ?624.45mhz ?738.45mhz ?130.45mhz ?374.60mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 21 31 1 51 61 41 figure 124 . high band wideband aclr 09616-186 sp an 54mhz sweep 1.49s vbw 3khz center 210mhz #res bw 30khz upper fi l ter off off off off off dbc ?58.78 ?73.56 ?75.42 ?78.08 ?79.06 dbm ?76.34 ?91.12 ?92.98 ?95.64 ?96.62 lower dbc ?1 1.15 ?0.454 ?0.065 ?0.091 ?53.44 dbm ?28.70 ?18.01 ?17.62 ?17.65 ?70.99 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?17.556dbm/6mhz acp-ibw 10db/div ?53.4dbc ?0.1dbc ?0.1dbc ?0.5dbc ?17.6dbm ?73.6dbc ?75.4dbc ?79.1dbc ?78.1dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figu re 125 . low band narrow - band aclr (worse side) 09616-187 sp an 54mhz sweep 1.49s vbw 3khz center 650mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.18 ?0.294 ?0.075 ?0.145 ?50.21 dbm ?30.68 ?19.80 ?19.58 ?19.65 ?69.71 lower dbc ?61.84 ?72.95 ?74.99 ?76.38 ?76.59 dbm ?81.35 ?92.45 ?94.49 ?95.89 ?96.10 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?19.503dbm/6mhz acp-ibw 10db/div ?76.4dbc ?75.0dbc ?72.9dbc ?19.5dbm ?0.3dbc ?0.1dbc ?50.2dbc ?0.1dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 ?76.6dbc figure 126 . mid band narrow - band aclr (worse side) 09616-188 sp an 54mhz sweep 1.49s vbw 3khz center 970mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.77 ?0.522 ?0.140 ?0.5 11 ?52.31 dbm ?31.44 ?21.19 ?20.81 ?21.18 ?72.98 lower dbc ?60.65 ?68.68 ?70.67 ?72.96 ?74.22 dbm ?81.32 ?89.34 ?91.33 ?93.63 ?94.89 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?20.666dbm/6mhz acp-ibw 10db/div ?73.0dbc ?70.7dbc ?68.7bc ?20.7dbm ?0.5dbc ?0.1dbc ?52.3dbc ?0.5dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 ?74.2dbc figure 127 . high band narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 35 of 64 eight - carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-189 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?22.044dbm ?71.492db ?70.555db ?68.566db ?65.237db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power () () () () () () () () () () () () y ?22.043dbm ?71.545db ?70.510db ?68.566db ?65.219db f f f f f 1 1 1 1 1 1 2 3 4 5 x n 1 1 1 1 mode mkr sc l trc 200mhz 216.60mhz 400mhz 621.30mhz 413.25mhz ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 31 51 21 41 1 figure 1 28 . low band wideband aclr 09616-190 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?23.977dbm ?69.185db ?68.551db ?69.938db ?72.083db ?65.009db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?23.977dbm ?69.185db ?68.551db ?69.923db ?72.145db ?65.009db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 667.80mhz ?171.30mhz ?98.15mhz ?614.00mhz ?567.45mhz ?55.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 31 21 41 1 61 51 figure 129 . mid band wideband aclr 09616-191 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?25.435dbm ?61.947db ?67.532db ?69.602db ?65.237db ?64.615db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?25.435dbm ?61.947db ?67.517db ?69.583db ?65.237db ?64.615db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 990.80mhz ?481.00mhz ?633.95mhz ?734.65mhz ?128.55mhz ?378.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 31 21 41 1 61 51 figure 130 . high band wideband aclr 09616-192 sp an 54mhz sweep 1.49s vbw 3khz center 222mhz #res bw 30khz upper fi l ter off off off off off dbc ?59.41 ?69.96 ?69.91 ?69.74 ?70.08 dbm ?81.28 ?91.83 ?91.78 ?91.62 ?91.95 lower dbc ?10.98 ?0.334 0.087 ?0.034 0.031 dbm ?32.85 ?22.21 ?21.79 ?21.91 ?21.84 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?21.874dbm/6mhz acp-ibw 10db/div 0.0dbc 0.0dbc 0.1dbc ?0.3dbc ?21.9dbm ?70.0bc ?69.9dbc ?70.1dbc ?69.7dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figure 131 . low band narrow - band aclr (worse side) 09616-193 sp an 54mhz sweep 1.49s vbw 3khz center 580mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.25 ?0.459 ?0.137 ?0.181 ?0.221 dbm ?33.80 ?23.01 ?22.69 ?22.74 ?22.78 lower dbc ?60.21 ?71.35 ?71.20 ?71.51 ?71.60 dbm ?82.77 ?93.90 ?93.75 ?94.06 ?94.16 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?22.556dbm/6mhz acp-ibw 10db/div ?71.6dbc ?71.5dbc ?71.2dbc ?71.3dbc ?22.6dbm ?0.5bc ?0.1dbc ?0.2dbc ?0.2dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figure 132 . mid band narrow - band aclr (worse side) 09616-194 sp an 54mhz sweep 1.49s vbw 3khz center 950mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.93 ?0.487 ?0.205 ?0.047 ?0.016 dbm ?36.27 ?25.83 ?25.55 ?25.39 ?25.33 lower dbc ?60.39 ?67.44 ?67.29 ?67.65 ?67.65 dbm ?85.73 ?92.78 ?92.63 ?93.00 ?93.00 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?25.344dbm/6mhz acp-ibw 10db/div ?67.7dbc ?67.7dbc ?67.3dbc ?67.4dbc ?25.3dbm ?0.5bc ?0.2dbc 0.0dbc 0.0dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figure 133 . high band narr ow - band aclr c
ad9737a/AD9739A data sheet rev. | page 36 of 64 16- carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-195 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?25.335dbm ?66.838db ?70.312db ?65.928db ?66.973db ?64.451db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?25.335dbm ?66.838db ?70.421db ?65.880db ?67.033db ?64.481db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 289.70mhz 202.05mhz ?183.65mhz 697.95mhz 18.70mhz 322.70mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 31 51 1 21 41 61 figure 134 . low band wideband aclr 09616-196 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?28.317dbm ?64.672db ?65.207db ?64.574db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?28.317dbm ?64.672db ?65.202db ?64.574db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 690.60mhz ?141.85mhz ?623.50mhz 152.65mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 1 21 41 31 figure 135 . mi d band wideband aclr 09616-197 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?27.960dbm ?61. 1 10db ?63.332db ?65.483db ?62.779db ?59.828db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power () () () () () () () () () () () () () () () y ?27.971dbm ?61. 1 10db ?63.327db ?65.509db ?62.779db ?59.858db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n 1 1 1 1 1 mode mkr sc l trc 989.85mhz ?422.10mhz ?922.75mhz ?668.15mhz ?137.10mhz ?377.45mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 31 51 41 61 1 21 figure 136 . high band wideband aclr 09616-198 sp an 54mhz sweep 1.49s vbw 3khz center 290mhz #res bw 30khz upper fi l ter off off off off off dbc ?59.93 ?70.37 ?69.75 ?69.75 ?69.79 dbm ?84.76 ?95.20 ?94.57 ?94.57 ?94.62 lower dbc ?10.83 ?0.545 ?0.099 ?0.155 ?0.041 dbm ?35.76 ?25.37 ?24.92 ?24.98 ?24.87 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?24.824dbm/6mhz acp-ibw 10db/div 0.0dbc ?0.2dbc ?0.1dbc ?0.5dbc ?24.8dbm ?70.4dbc ?69.7dbc ?69.8dbc ?69.7dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 figure 137 . low band narrow - band aclr 09616-199 sp an 54mhz sweep 1.49s vbw 3khz center 690mhz #res bw 30khz upper fi l ter off off off off off dbc ?58.12 ?67.47 ?66.83 ?66.80 ?66.79 dbm ?84.92 ?94.26 ?93.62 ?93.59 ?93.58 lower dbc ?1 1.17 ?0.460 ?0.049 ?0.196 ?0.366 dbm ?37.97 ?27.25 ?26.74 ?26.60 ?26.43 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?26.792dbm/6mhz acp-ibw 10db/div 0.4dbc 0.2dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 0.0dbc ?0.5dbc ?26.8dbm ?67.5dbc ?66.8dbc ?66.8dbc ?66.8bc figure 138 . mid band narrow - band aclr (worse side) 09616-200 sp an 54mhz sweep 1.49s vbw 3khz center 900mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.30 ?0.490 ?0. 1 19 ?0.016 0.153 dbm ?39.73 ?28.92 ?28.55 ?28.45 ?28.28 lower dbc ?57.24 ?65.03 ?64.64 ?64.80 ?64.86 dbm ?85.68 ?93.46 ?93.08 ?93.24 ?93.29 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?28.435dbm/6mhz acp-ibw 10db/div ?64.8dbc ?64.6dbc ?65.0dbc ?28.4dbm ?0.5dbc ?0.1dbc 0.2dbc 0.0dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?64.9dbc figure 139 . high band narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 37 of 64 32- carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-201 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?29.645dbm ?64.167db ?59.423db ?62.750db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?29.646dbm ?64.175db ?59.429db ?62.750db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 384.70mhz ?283.40mhz 227.70mhz 325.55mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 1 41 21 31 figure 140 . low band wideband aclr 09616-202 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?30.335dbm ?63. 1 12db ?63.860db ?62.151db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?30.335dbm ?63.136db ?63.860db ?62.151db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 685.5mhz ?6 1 1.15mhz ?243.50mhz 162.15mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 21 31 1 41 figur e 141 . mid band wideband aclr 09616-203 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?31.516dbm ?59.997db ?60.535db ?57.763db 6mhz 6mhz 6mhz 6mhz band power band power band power band power () () () () () () () () () y ?31.516dbm ?59.997db ?60.458db ?57.761db f f f f 1 1 1 1 1 2 3 4 x n 1 1 1 mode mkr sc l trc 985.10mhz ?334.70mhz ?909.45mhz ?373.65mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 1 31 41 21 figure 142 . high band wideband aclr 09616-204 sp an 54mhz sweep 1.49s vbw 3khz center 386mhz #res bw 30khz upper fi l ter off off off off off dbc ?61.86 ?65.40 ?64.76 ?64.50 ?64.40 dbm ?91.78 ?95.32 ?94.68 ?94.42 ?94.32 lower dbc ?10.67 ?0.431 ?0.070 ?0.0 11 0. 1 16 dbm ?40.59 ?30.35 ?29.99 ?29.93 ?29.80 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?29.920dbm/6mhz acp-ibw 10db/div 0.1dbc 0.0dbc ?0.1dbc ?0.4dbc ?29.9dbm ?65.4dbc ?64.8dbc ?64.4dbc ?64.5dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 figure 143 . low band narrow - band aclr 09616-205 sp an 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.78 ?0.487 ?0.175 ?0.151 ?0.061 dbm ?40.09 ?29.80 ?29.49 ?29.46 ?29.37 lower dbc ?58.76 ?63.30 ?63.05 ?63.21 ?64.46 dbm ?88.07 ?92.61 ?92.36 ?92.52 ?92.78 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?29.3 1 1dbm/6mhz acp-ibw 10db/div ?63.2dbc ?63.1dbc ?63.3dbc ?29.3dbm ?0.5dbc ?0.2dbc ?0.1dbc ?0.2dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?63.5dbc figure 144 . mid band narrow - band aclr ( worse side) 09616-206 sp an 54mhz sweep 1.49s vbw 3khz center 800mhz #res bw 30khz upper fi l ter off off off off off dbc ?10.84 ?0.437 ?0.354 ?0.455 ?0.410 dbm ?41.59 ?31.18 ?31.10 ?31.20 ?31.16 lower dbc ?60.75 ?63.18 ?62.76 ?62.74 ?62.84 dbm ?91.49 ?93.92 ?93.50 ?93.48 ?93.59 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?30.746dbm/6mhz acp-ibw 10db/div ?62.7dbc ?62.8dbc ?63.2dbc ?30.7dbm ?0.4dbc ?0.4dbc ?0.4dbc ?0.5dbc ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?62.8dbc figure 145 . high band narrow - band aclr c
ad9737a/AD9739A data sheet rev. | page 38 of 64 64- and 128- carrier docsis perfo rmance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, t a = 25c , unless otherwise noted. 09616-219 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?33.209dbm ?58.804db ?55.165db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?33.210dbm ?58.746db ?55.165db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 478.75mhz 372.10mhz 132.70mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 1 31 21 figure 146 . 64 - carrier low band wideband aclr 09616-220 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?35.873dbm ?58.625db ?59.286db 6mhz 6mhz 6mhz band power band power band power () () () () () () y ?35.872dbm ?58.5816db ?59.214db f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 978.45mhz ?901.85mhz ?561.75mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 1 21 31 figure 147 . 64 - carrier high band wideband aclr 09616-221 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) st art 50mhz #res bw 20khz function v alue function width function ?35.495dbm ?55.328db ?37.545dbm 6mhz 6mhz 6mhz band power band power band power () () () y ?35.495dbm ?55.328db ?37.544dbm f f f 1 1 1 1 2 3 x n 1 1 mode mkr sc l trc 69.00mhz 855.95mhz 831.85mhz ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 1 3 21 figure 148 . 128 - carrier wideband aclr 09616-222 sp an 54mhz sweep 1.49s vbw 3khz center 478mhz #res bw 30khz upper fi l ter off off off off off dbc ?60.80 ?62.25 ?61.47 ?61.54 ?61.40 dbm ?93.21 ?94.66 ?93.88 ?93.95 ?93.81 lower dbc ?10.83 ?0.267 0.139 0.201 0.308 dbm ?43.24 ?32.68 ?32.27 ?32.21 ?32.10 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?32.409dbm/6mhz acp-ibw 10db/div 0.3dbc 0.2dbc 0.1dbc ?0.3dbc ?32.4dbm ?62.3dbc ?61.5dbc ?61.4dbc ?61.5dbc ?51 ?61 ?71 ?81 ?91 ?101 ?111 ?121 ?131 figure 149 . 64 - carrier low band narrow - band aclr 09616-223 sp an 54mhz sweep 1.49s vbw 3khz center 600mhz #res bw 30khz upper fi l ter off off off off off dbc ?1 1.48 ?0.284 0.099 0.221 0.060 dbm ?45.04 ?33.84 ?33.46 ?33.34 ?33.50 lower dbc ?60.02 ?61. 11 ?60.57 ?60.64 ?60.58 dbm ?93.58 ?94.66 ?94.13 ?94.20 ?94.14 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?33.558dbm/6mhz acp-ibw 10db/div ?60.6dbc ?60.6dbc ?60.6dbc ?61.1dbc ?33.6dbm ?0.3dbc ?0.1dbc 0.1dbc 0.2dbc ?51 ?61 ?71 ?81 ?91 ?101 ?111 ?121 ?131 figure 150 . 64 - carrier high band narrow - band aclr 09616-224 sp an 54mhz sweep 1.49s vbw 3khz center 832mhz #res bw 30khz upper fi l ter off off off off off dbc ?59.34 ?57.70 ?56.56 ?56.49 ?56.35 dbm ?96.67 ?95.03 ?93.89 ?93.82 ?93.69 lower dbc ?10.77 ?0.277 0.318 0.328 0.337 dbm ?48.10 ?37.61 ?37.01 ?37.00 ?37.00 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?37.33dbm/6mhz acp-ibw 10db/div 0.3dbc 0.3dbc 0.3dbc ?0.3dbc ?37.3dbm ?57.7dbc ?56.6dbc ?56.4dbc ?56.5dbc ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 151 . 128 - carrier narrow - band aclr c
data sheet ad9737a/AD9739A rev. | page 39 of 64 terminology linearity error (integral nonlinearity or inl) the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. differential nonlinearity (dnl) the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. mo notonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of 0 is called the offset error. for ioutp, 0 ma output is expected when the in puts are all 0s. for ioutn, 0 ma output is expected when all inputs are set to 1. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperatur e drift specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full - scale output as the supplies are varied from nominal to minimum and maximum specified voltages. spurious - free dynamic range the difference, in decibels (db), between the rms amplitude of the output sig nal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). noise spectral density (nsd) nsd is the converter noise power per unit of bandwidth. this is usually specified in dbm/hz in the presence of a 0 dbm full - scale signal. adjacent channel leakage ratio (aclr) the adjacent channel leakage (power) ratio is a r atio, in dbc, of the measured power within a channel relative to its adjacent channels. modulation error ratio (mer) modulated signals create a discrete set of output values referred to as a constellation. each symbol creates an output signal correspondin g to one point on the constellation. mer is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. intermodulation distortion (imd) imd is the result of two or more signals at different frequencies mixing together. many products are created according to the formula, af1 bf2, where a and b are integer values. c
ad9737a/AD9739A data sheet rev. | page 40 of 64 serial port interface (spi) register spi register map des cription the ad9737a / AD9739A contain a set of programmable registers , described in table 10 , that are used to configure and monitor various internal parameters. note the following points w hen programming the ad9737a / AD9739A spi registers: ? registers pertaining to similar functions are grouped t o gether and assigned adjacent addresses. ? bits that are un defined within a register should be assigned a 0 when writing to that register. ? registers that are undefined should not be written to. ? a hardware or software reset is recommended on power - up to place spi registers in a known state. ? a spi initialization rou tine is required as part of the boot process. see table 29 for an example procedure. reset issuing a hardware or software reset places the ad9737a / AD9739A spi registers in a known state. all spi registers (excluding 0x00) are set to their default states , as described in table 10, upon issuing a reset. after issuing a reset, the spi initialization p rocess need s only to write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application. although the ad9737a / AD9739A do feature an internal power - on reset (por), it is still recommended that a software or hardware reset be implemented shortly after power - up. the internal reset signal is derived from a logical or operation from the internal por signal, the reset pin, and the software reset state. a software reset can be issued via the reset bit (register 0x00, bit 5) by toggling the bit high , then low. note that, because the msb/lsb format may still be unknown upon initial power - up (that is, internal por is unsuccessful), it is also recommended that the bit settings for bits[7:5] be mirrored onto bits[2:0] for the instruction cycle that issues a software reset. a hardware reset can be issued from a host or external supervisory ic by applying a high pulse with a minimum width of 40 ns to the reset pin (that is, pin f14). reset should be tied to vss if unused. table 9 . spi registers pertaining to spi options address (hex) bit description 0x00 7 enable 3 - wire spi 6 enable spi lsb first 5 software reset spi operation the serial port of the ad9737a / AD9739A , shown in figure 152, has a 3 - or 4 - wire spi capability, allowing read/write access to all registers that configure the devices internal parameters. it provides a flexible, synchronous serial communications port, allowing easy interface to many industry - standard micro controllers and microprocessors. the 3.3 v serial i/o is compatible with most synchronous transfer formats, including the motorola? spi and the intel? ssr protocols. sdo (pin h14) sdio (pin g14) sclk (pin h13) cs (pin g13) ad9737a/ad9739 a spi port 09616-072 figure 152 . ad97 37a / AD9739A spi port the default 4 - wire spi interface consists of a clock (sclk), serial port enable ( cs ), serial data input (sdio), and serial data output (sdo). the inputs to sclk , cs , and sdio contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about vdd33/2. the maximum frequency for sclk is 20 mhz. the sdo pin is active only during the transmission of data and remains three - stated at any other time . a 3 - wire spi interface can be enabled by setting the sdio_dir bit (register 0x00, bit 7). this causes the sdio pin to become bidirectional such that output data appears on only the sdio pin during a read operation. the sdo pin remains three - stated in a 3 - wire spi interface. instruction header information msb lsb 17 16 15 14 13 12 11 10 r/ w a6 a5 a4 a3 a2 a1 a0 an 8 - bit instruction header must accompany each read and write operation. the msb is a r/ w indicator bit wit h logic high indicating a read operation. the remaining seven bits specify the address bits to be accessed during the data transfer portion. the eight data bits i m mediately follow the instruction header for both read and write operations. for write operati ons, registers change immediately upon writing to the last bit of each transfer byte. cs can be raised after each sequence of eight bits (except the last byte) to stall the bus. the serial transfer resumes when cs is low ered. stalling on nonbyte boundaries resets the spi. c
data sheet ad9737a/AD9739A rev. | page 41 of 64 the ad9737a / AD9739A serial port can support both most significant bit (msb) first and least significant bit (lsb) first data formats. figure 153 illu s trates how the serial port words are formed for the msb first and lsb first mode s. the bit order is controlled by the lsb/msb bit (register 0x00, bit 6 ). the default value o f bit 6 is 0, msb first. when the lsb /msb bit is set high, the serial port interprets both instruction and data bytes lsb first. scl k sdata scl k sdata r/w r/w a1 a3 a2 a4 n1 n1 n2 n2 a0 a3 a1 a2 a0 a4 d7 1 d0 1 d1 1 d6 n d7 n d6 1 d1 n d0 n data transfer cycle instruction cycle data transfer cycle instruction cycle 09616-073 cs cs figure 153 . spi timing, msb first (upper) and lsb first (lower) figure 154 illustrates the timing requirements for a write oper a tion to the spi port. after the serial port enable ( cs ) signal goes low, data (sdio) pertaining to the instruction header is read on the rising edges of the clock (scl k ) . to initiate a write operation, the read/not - write bit is set low. after the instruction header is read, the eight data bits pertaining to the specified register are shifted into the sdio pin on the rising edge of the next eight clock cycles. figure 155 illustrates the timing for a 3 - wire read operation to the spi port. after cs goes low, data (sdio) pertaining to the instruction header is read on the rising edges of sclk. a read operation occur s if the read/not - write indicator is set high. after the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the sdio pin on the falling edges of the next eight clock c ycles. figure 156 illustrates the timing for a 4 - wire read operation to the spi port. the timing is similar to the 3 - wire read operation with the exception that data appears at the sdo pin only, whereas the sdio pin remains at hi gh impedance throughout the operation. the sdo pin is an active output only during the data transfer phase and remains three - stated at all other times. d7 d6 a0 d1 n1 n0 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w d0 t h 09616-074 cs figure 154 . spi write operation timing d7 d6 a0 d1 n1 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w d0 t ez a2 a1 t dv 09616-075 cs figure 155 . spi 3 - wire read operation timing a0 cs n1 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w t ez a2 a1 t dv d7 d6 d1 sdo d0 t ez 09616-076 figure 156 . spi 4 - wire read operation timing c
ad9737a/AD9739A data sheet rev. | page 42 of 64 spi register map table 10. full register map (n/a = not applicable) name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 default mode 0x00 sdio_dir lsb/msb reset n/a n/a n/a n/a n/a 0x00 power - down 0x01 n/a n/a lvds_ drvr _pd lvds_ rcvr_pd n/a n/a clk_rcvr_ pd dac_bias_ pd 0x00 cnt_clk_ d is 0x02 n/a n/a n/a n/a clkgen_pd n/a rec_cnt_ clk mu_cnt_ clk 0x03 irq_e n 0x03 n/a n/a n/a n/a mu_lst_en mu_lck_en rcv_lst_en rcv_lck_e n 0x00 irq_r eq 0x04 n/a n/a n/a n/a mu_lst_irq mu_lck_irq rcv _ lst_ irq rcv _ lck_ irq 0x00 rsvd 0x05 n/a n/a n/a n/a n/a n/a n/a n/a n/a fsc_1 0x06 fsc[7] fsc[6] fsc[5] fsc[4] fsc[3] fsc[2] fsc[ 1] fsc[0] 0x00 fsc_2 0x07 sleep n/a n/a n/a n/a n/a fsc[9] fsc[8] 0x02 d ec _cnt 0x08 n/a n/a n/a n/a n/a n/a dac_dec[1] dac_dec[0] 0x00 rsvd 0x09 n/a n/a n/a n/a n/a n/a n/a n/a n/a lvds_cnt 0x0a n/a n/a n/a n/a n/a n/a n/a n/a 0x00 dig_stat 0x0b n/a n /a n/a n/a n/a n/a n/a n/a rndm lvds_stat1 0x0c sup/hld_ edge1 n/a dci_phs3 dci_phs1 dci_pre_ ph2 dci_pre_ ph0 dci_pst_ ph2 dci_pst_ ph0 rndm lvds_stat2 0x0d n/a n/a n/a n/a n/a n/a n/a n/a r ndm/0 rsvd 0x0e n/a n/a n/a n/a n/a n/a n/a n/a n/a rsvd 0x0f n/a n/a n/a n/a n/a n/a n/a n/a n/a lvds_ rec_cnt1 0x10 n/a n/a n/a n/a n/a rcvr_flg_ rst rcvr_ loop_on rcvr_cnt_ ena 0x42 lvds_ rec_cnt2 0x11 smp_del[1] smp_del[0] n/a n/a n/a n/a n/a n/a 0xdd lvds_ rec_cnt3 0x12 smp_del[9] smp_del[8] smp_del[7] smp_del [6] smp_del[5] smp_del[4] smp_del[3] smp_del[2] 0x29 lvds_ rec_cnt4 0x13 dci_del[3] dci_del[2] dci_del[1] dci_del[0] fine_del_ skw[3] fine_del_ skw[2] fine_del_ skw[1] fine_del_ skw[0] 0x71 lvds_ rec_cnt5 0x14 n/a n/a dci_del[9] dci_del[8] dci_del[7] dci _del[6] dci_del[5] dci_del[4] 0x0a lvds_ rec_cnt6 0x15 n/a n/a n/a n/a n/a n/a n/a n/a 0x42 lvds_ rec_cnt7 0x16 n/a n/a n/a n/a n/a n/a n/a n/a 0x00 lvds_ rec_cnt8 0x17 n/a n/a n/a n/a n/a n/a n/a n/a 0x00 lvds_ rec_cnt9 0x18 n/a n/a n/a n/a n/a n/a n/ a n/a 0x00 lvds_ rec_stat1 0x19 smp_del[1] smp_del[0] n/a n/a n/a n/a n/a n/a 0xc7 lvds_ rec_stat2 0x1a smp_del[9] smp_del[8] smp_del[7] smp_del[6] smp_del[5] smp_del[4] smp_de l [3] smp_del[2] 0x29 lvds_ rec_stat3 0x1b dci_del[1] dci_del[0] n/a n/a n/a n /a n/a n/a 0xc0 lvds_ rec_stat4 0x1c dci_del[9] dci_del[8] dci_del[7] dci_del[6] dci_del[5] dci_del[4] dci_del[3] dci_del[2] 0x29 lvds_ rec_stat5 0x1d n/a n/a n/a n/a n/a n/a n/a n/a 0x86 lvds_ rec_stat6 0x1e n/a n/a n/a n/a n/a n/a n/a n/a 0x00 lvds_ rec_stat7 0x1f n/a n/a n/a n/a n/a n/a n/a n/a 0x00 lvd s_ rec_stat8 0x20 n/a n/a n/a n/a n/a n/a n/a n/a 0x00 lvds_ rec_stat9 0x21 n/a n/a n/a n/a rcvr_trk_ on rcvr_fe_ on rcvr_lst rcvr_lck 0x00 cross_ cnt1 0x22 n/a n/a n/a dir_p clkp_ offset[3] clkp_ of fset[2] clkp_ offset[1] clkp_ offset[0] 0x00 c
data sheet ad9737a/AD9739A rev. | page 43 of 64 name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 default cross_ cnt2 0x23 n/a n/a n/a dir_n clkn_ offset[3] clkn_ offset[2] clkn_ offset[1] clkn_ offset[0] 0x00 phs_det 0x24 n/a n/a cmp_bst phs_det auto_en n/a n/a n/a n/a 0x00 mu_duty 0x25 mu_ dutyauto_ en pos/neg adj[5] adj[4] n/a n/a n/a n/a 0x00 mu_cnt1 0x26 n/a slope mode[1] mode[0] read gain[1] gain[0] enable 0x42 mu_cnt2 0x27 mudel[0] srch_ mode[1] srch_ mode[0] set_phs[4] set_phs[3] set_phs[2] set_phs[1] set_phs[0] 0x40 mu_cnt3 0x28 mudel[8] mudel[7] mudel [6] mudel[5] mudel[4] mudel[3] mudel[2] mudel[1] 0x00 mu_cnt4 0x29 search_tol retry contrst guard[4] guard[3] guard[2] guard[1] guard[0] 0x0b mu_stat1 0x2a n/a n/a n/a n/a n/a n/a mu_lost mu_lkd 0x00 rsvd 0x2b n/a n/a n/a n/a n/a n/a n/a n/a n/a rsvd 0 x2c n/a n/a n/a n/a n/a n/a n/a n/a n/a ana_cnt1 0x32 n/a n/a n/a n/a n/a n/a n/a n/a 0xca ana_cnt2 0x33 n/a n/a n/a n/a n/a n/a n/a n/a 0x03 rsvd 0x34 n/a n/a n/a n/a n/a n/a n/a n/a n/a part_id 0x35 id[7] id[6] id[5] id[4] id[3] id[2] id[1] id[0] 0x4 0 spi port configuration and software rese t table 11. spi port configuration and software reset register (mode) address (hex) bit name bit s r/w default setting description 0x00 sdio_dir 7 r/w 0 x0 0 = 4 - wire spi, 1 = 3 - wire spi. lsb/msb 6 r/w 0x0 0 = msb first, 1 = lsb first. reset 5 r/w 0x0 software reset is recommended before modification of other spi registers from the default setting. 0 = inactive state; allows the user to modify registers from the default setting. 1 = caus es all registers (except 0x00) to be set to the default setting. power - down lvds interface and tx dac ? table 12. power- down lvds interface and txdac reg ister (power- down) address (hex) bit name bit s r/w default setting description 0x01 lvds_drvr_pd 5 r/w 0 x0 power - down of the lvds drivers/receivers and txdac. 0 = enable, 1 = disable. lvds_rcvr_pd 4 r/w 0x0 clk_rcvr_pd 1 r/w 0x0 dac_bias_pd 0 r/w 0 x0 controller clock dis able table 13. controller cl ock disable register (cnt_clk_d is ) address (hex) bit name bit s r/w default setting description 0x02 clkgen_pd 3 r/w 0x 0 internal clk distribution enable: 0 = enable, 1 = disable. rec_cnt_clk 1 r/w 0x1 lvds receiver and mu controller clock disable. 0 = d isable, 1 = enable. mu_cnt_clk 0 r/w 0x1 c
ad9737a/AD9739A data sheet rev. | page 44 of 64 interrupt request (irq) enable/status table 14. interrupt request (irq) enable ( irq_e n)/ status (irq_r eq) register address (hex) bit name bit s r/w default setting description 0x03 mu_lst_en 3 w 0x0 this register enables the mu and lvds rx controllers to update their corresponding irq status bits in register 0x04, which defines whether the controller is locked (lck) or unlocked (lst). 0 = disable (resets the status bit), 1 = enable. mu_lck_en 2 w 0x0 rcv_lst_en 1 w 0x0 rcv_lck_en 0 w 0x0 0x04 mu_lst_irq 3 r 0x0 this register indicates the status of the controllers. for lck_ir q bits: 0 = lock lost , 1 = locked. for lst_ir q bits: 0 = lock not lost, 1 = unlocked. note that, if the controller irq is serviced, the relevant bits in register 0x03 should be reset by writing 0, followed by another write of 1 to enable. mu_lck_irq 2 r 0x0 rcv_lst_irq 1 r 0x0 rcv_lck_irq 0 r 0x0 tx dac full - scale curr ent setting (i outfs ) and sleep table 15. txdac full - scale current setting (i outfs ) and sleep register (fsc_1 and fsc_2) address (hex) bit name bit s r/w default setting description 0x06 fsc[7:0] [7:0] r/w 0x00 sets the txdac i outfs current between 8 ma and 31 ma (default = 20 ma). i outfs = 0.0226 fsc[9:0] + 8.58, where fsc = 0 to 1023. 0x07 fsc[9:8] [1:0] r/w 0x02 sleep 7 r/w 0 = enable dac output, 1 = disable dac output (sleep). tx dac quad - switch mode of opera tion table 16. txdac q uad - switch mode of operation register (d ec_cnt) address (hex) bit name bit s r/w default setting description 0x08 dac _dec [1:0] r/w 0x00 0x00 = normal baseband mode. 0x02 = mix - mode . dci phase alignment status table 17. dci phase a lignment status register (lvds_stat1) address (hex) bit name bit s r/w default setting description 0x0c dci_pre_ph0 2 r 0x0 0 = dci rising edge is after the pre delayed version of the phase 0 sampling edge. 1 = dci rising edge is before the pre delayed ver sion of the phase 0 sampling edge. dci_pst_ph0 0 r 0x0 0 = dci rising edge is after the post delayed version of the phase 0 sampling edge. 1 = dci rising edge is before the post delayed version of the phase 0 sampling edge. data receiver contro ller conf iguration table 18. data receiver controller configuration register (lvds_rec_cnt1) address (hex) bit name bit s r/w default setting description 0x10 rcvr_flg_rst 2 w 0x0 data receiver controller flag reset. write 1 followed by 0 t o reset flags. rcvr_loop_on 1 r/w 0x 1 0 = disable, 1 = enable. when this bit is enabled, the data receiver controller generates an irq; it falls out of lock and automatically begins a search/track routine. rcvr_cnt_ena 0 r/w 0x 0 data receiver controll er enable. 0 = disable, 1 = enable. c
data sheet ad9737a/AD9739A rev. | page 45 of 64 dat a receiver controlle r_data sample delay value table 19. data receiver controller_data sample delay value register (lvds_ rec_cnt2 and lvds_rec_cnt3) address (hex) bit name bit s r/w default setting description 0x11 smp_del[1:0] [7:6] r/w 0x11 controller enabled: the 10 - bit value (with a maximum of 384) represents the start value for the delay line used by the state machine to sample data. leave at the default setting of 167, which is near the midpoint of the delay line. controller disabled: the value sets the actual value of the delay line. 0x12 smp_del[9:2] [7:0] r/w 0x25 data receiver contro ller_dci delay value /window and phase ro tation table 20. data receiver contr oller_dci delay valu e (lvds_rec_cnt4) /window and phase rotation register (lvds_rec_cnt5) address (hex) bit name bit s r/w default setting description 0x13 dci_del[3:0] [7:4] r/w 0x0111 refer to the dci_del description in register 0x14. fine_del_ skw[3:0] [3:0] r/w 0x0001 a 4- bit value sets the difference (that is, window) for the dci pre and post sampling clocks. leave at the default value of 1 for a narrow window. 0x14 dci_del[9:4] [5:0] r/w 0x001010 controller enabled: the 10 - bit value (with a maximum of 384) represents the start value for the delay line used by the state machine to sample the dci input. leave at the default setting of 167, which is near the midpoint of the delay line. controller disabled: the value sets the actual value of the delay line. data receiver contro ller_delay line stat us table 21. data receiver controller_delay line status register (lvds_rec_stat[1:4]) address (hex) bit name bit s r/w default setting description 0x19 smp_del[1:0] [7:6] r 0x00 the actual value of the dci and data delay lines are determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. note that these values should be equal. 0x1a smp_del[9:2] [7:0] r 0x00 0x1b dci_d el[1:0] [7:6] r 0x 00 0x1c dci_del[9:2] [7:0] r 0x00 data receiver contro ller lock/tracking s tatus table 22. data receiver controller lock/tracking status register (lvds_rec_stat9) address (hex) bit name bit s r/w default setting description 0x21 rcvr_trk_on 3 r 0x 0 0 = tracking not established, 1 = tracking established. rc v r_f e _on 2 r 0x 0 0 = f ind e dge s tate m achine is not active, 1 = f in d e dge s tate m achine is active. rcvr_lst 1 r 0 x0 0 = controller has not lost lock, 1 = co ntroller has lost lock. rcvr_lck 0 r 0 x0 0 = controller is not locked, 1 = controller is locked. c
ad9737a/AD9739A data sheet rev. | page 46 of 64 clk input common mod e table 23. clk input common mode register (cross_cnt1 and cross_cnt2) address (hex) bit name bit s r/w default setting description 0x22 dir_p 4 r/w 0x 0 dir_p and dir_n. 0 = vcm at the dacclk_p input decreases with the offset value. 1 = vcm at the dacclk_p input increases with the offset value. clkx_offset sets the magnitude of the offset for the dacclk_p and dacc lk_n inputs. for optimum performance, set to 1111. clkp_offset[3:0] [3:0] r/w 0x0000 0x23 dir_n 4 r/w 0x 0 clkn_offset[3:0] [3:0] r/w 0x 0000 mu controller config uration and status table 24. mu controller configuration and st atus register (phs_det , mu_duty , mu_cnt [1:4 ] , and mu _ stat1) address (hex) bit name bit s r/w default setting description 0x24 cmp_bst 5 r/w 0x 0 phase detector enable and boost bias bits. note that both bits should always be set to 1 to enable these functi ons. phs_det auto_en 4 r/w 0x 0 0x25 mu_ dutyauto_en 7 r/w 0x 0 mu controller duty cycle enable. note that this bit should always be set to 1 to enable. 0x26 slope 6 r/w 0x 1 mu controller phase slope lock. 0 = negative slope, 1 = positive slope. note t hat a setting of 0 is recommended for best ac performance. mode[1:0] [5:4] r/w 0x00 sets the mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track. read 3 r/w 0x 0 set to 1 to read the current value of the m u delay line in. gain[1:0] [2:1] r/w 0x 01 sets the mu controller tracking gain. recommended to leave at the default 01 setting. enable 0 r/w 0x 0 0 = enable the mu controller. 1 = disable the mu controller. 0x27 mudel[0] 7 r/w 0x 0 the lsb of the 9 - bit mudel setting. srch_mode[1:0] [6:5] r/w 0x 0 sets the direction in which the mu controller searches (from its initial mudel setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, set_phs and slope ). 00 = down. 01 = up. 10 = down/up (recommended). set_phs[4:0] [4:0] r/w 0x 0 sets the target phase that the mu controller locks to with a maximum setting of 16. a setting of 4 (that is, 00100) is recommended for optimum ac performance. 0x28 mudel[8:1] [7: 0] w 0x00 with enable (bit 0, register 0x26) set to 0, this 9 - bit value represents the value that the mu delay is set to. note that the maximum value is 432. with enable set to 1, this value represents the mu delay value at which the controller begins its search. setting this value to the delay line midpoint of 216 is recommended. r 0x00 when read (bit 3, register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the mu controller l ocks to when enable = 1. 0x29 search_tol 7 r/w 0x 0 0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting). retry 6 r/w 0x 0 0 = stop the search if the correct value is not fou nd, 1 = retry the search if the correct value is not found. contrst 5 r/w 0x 0 controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting), 1 = reset. c
data sheet ad9737a/AD9739A rev. | page 47 of 64 address (hex) bit name bit s r/w default setting description guard[4:0] [4:0] r/w 0x01011 sets a g uard band from the beginning and end of the mu delay line , which the mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is decimal 11 or 0x0b). 0x2a mu_l o st 1 r 0x 0 0 = mu controller has not lost lock. 1 = mu controller has lost lock. mu_lkd 0 r 0x 0 0 = mu controller is not locked. 1= mu controller is locked. part id table 25. part id register (part_id) address (hex) bit name bit s r/w default setting description 0x35 id [ 7:0] [7:0] r 0x24 0x24 AD9739A 0x27 0x27 ad9737a c
ad9737a/AD9739A data sheet rev. | page 48 of 64 theory of operation the AD9739A and the ad9737a are 14 - and 11 - bit txdac s with a specified update rate of 1.6 gsps to 2.5 gsps. figure 157 shows a top - level functional diagram of the ad9737a / AD9739A . a high performance txdac core delivers a signal dependent, differential current (nominal 10 ma) to a balanced load referenced to ground. the frequency of the clock signal appearing at the ad9737a / AD9739A differential clock receiver, dacclk, sets the txdacs update rate. this clock signal, which serves as the master clock, is routed directly to the tx dac as well as to a clock distribution block that generates all critical internal and external clocks. the ad9737a / AD9739A include two lvds data ports (db0 and db1 ) to reduce the data interface rate to ? the txdac update rate. the host processor drives deinterleaved data with offset binary format onto the db0 and db1 ports, along with an embedded dci clock that is synchronous with the data. because the interface is double data rate (ddr), the dci clock is essentially an alternating 0 - 1 bit pattern with a frequency that is equal to ? the txdac update rate ( f dac ). to simplify synch - ronization with the host processor, the a d9737a / AD9739A passes an lvds clock output (dco) that is also equal to the dci frequency. the ad9737a / AD9739A data receiver controller generates an internal sampling clock for the ddr receiver such that the data instance sampling is optimized. when enabled and configured properly for track mode, it ensures proper data recovery between the host and the ad9737a / AD9739A clock domains. the data receiver controller has the ability to track several hundreds of p icoseconds of drift between these clock domains, typically caused by suppl y and temperature variation. as mentioned, the host processor provides the ad9737a / AD9739A with a deinterleaved data stream such that the db0 and db1 data ports r eceive alternating samples (that is, odd/even data streams). the ad9737a / AD9739A data assembler is used to reassemble (that is, multiplex) the odd/even data stream s into their original order before delivery into the txdac for signal reconstruction. the pipeline delay from a sample being latched into the data port to when it appears at the dac output is on the order of 78 () dacclk cycles. the ad9737a / AD9739A includes a delay lock loop (dll) circuit controlled via a mu controller to optimize the timing hand - off between the ad9737 a / AD9739A digital clock domain and txdac core. besides ensuring proper data reconstruction, the txdacs ac performance is also dependent on this critical hand - off between these clock domains with speeds of up to 2.5 gsps. once properly initialized and configured for track mode, the dll maintains optimum timing alignment over temperature , time, and power supply variation. a spi interface is used to configure the various functional block s as well as monitor their status for debug purposes. proper operation of the ad9737a / AD9739A requires that controller blocks be initialized upon power - up. a simple spi initialization routi ne is used to configure the controller blocks (see table 28). an irq output signal is available to alert the host should any of the controllers fall out of lock during normal operation. the following sections discu ss the various functional blocks in more detail as well as their implications when interfacing to external ics and circuitry. although a detailed description of the various controllers (and associated spi registers used to configure and monitor) is also included for completeness, the recommended spi boot procedure can be used to ensure reliable operation. lvds ddr receiver dci sdo sdio sclk cs dacclk dco db0[13:0] db1[13:0] clk distribution (div-by-4) data controller 4-to-1 data assembler spi reset dll (mu controller) lvds ddr receiver data latch ioutn ioutp vref i120 irq 1.2v dac bias ad9737a/AD9739A txdac core 09616-077 figure 157 . functional block diagram of the ad9737a / AD9739A c
data sheet ad9737a/AD9739A rev. | page 49 of 64 lvds data port interface the ad9737a / AD9739A supports input data rates from 1.6 gsps to 2.5 gsps using dual lvds data ports. the interface is source synchronous and double data rat e (ddr) where the host provides an embedded data clock input (dci) at f dac /4 with its rising and falling edges aligned with the data transitions. the data format is offset binary; however, twos complement format can be realized by reversing the polarity of the msb differential trace. as shown in figure 158 , the host feeds the ad9737a / AD9739A with deinterleaved input data in to two 11- bit lvds data ports (db0 and db1) at ? the dac clock rate (that is, f dac / 2). the ad9737a / AD9739A internal data receiver controlle r then generates a phase shifted version of dci to register the input data on both the rising and falling edges. lvds ddr receiver dci dco db0[13:0] div-by-4 data controller lvds ddr receiver db1[13:0] ad9737a/AD9739A host processor lvds ddr driver 14 2 f data = f dac /2 f dco = f dac /4 f dac f dci = f dac /4 14 2 1 2 1 2 data deinterleaver even data samples odd data samples 09616-078 figure 158 . recommended digital interface between the ad9737a / AD9739A and host processor as shown in figure 159 , the dci clock edges must be coincident with the data bit transitions with minimum skew, jitter, and i ntersymbol interference. to ensure coincident t ransitions with the data bits, the dci signal should be implemented as an additional data line with an alternating (010101) bit sequence from the same output drivers used for the data. maximizing the opening of the eye in both the dci and data signals imp roves the reliability of the data port interface. differential controlled impedance traces of equal length (that is, delay) should also be used between the host processor and ad9737a / AD9739A input to limit bit - to - bit skew. the maximum allowable skew and jitter out of the host processor with respect to the dci clock edge on each lvds port is calculated as follows: maxskew + jitter = period ( ps) ? validwindow (ps) ? guard = 800 ps ? 344 ps ? 100 ps = 356 ps where validwindow (ps) is represented by t va l i d and guard is represented by t guard in figure 159. the minimum specified lvds valid window is 344 ps , and a guard band of 100 ps is recommended. therefore, at the maxi - mum operating frequency of 2.5 gsps, the maximum allowable fpga and pcb bit skew plus jitter is equal to 356 ps. for synchronous operation, the ad9737a / AD9739A provides a data clock output, dco, to the host at the same rate as dci (that is, f dac /4) to maintain the lowest skew variation between these clock domains. the host processor has a worst cas e skew between dco and dci that is both implementation and process dependent. this worst case skew can also vary an additional 30% over temperature and supply corners. the delay line within the data receiver controller can track a 1.5 ns skew variation af ter initial lock. while it is possible for the host to have an internal pll that generates a synchronous f dac /4 from which the dci signal is derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation . the data receiver controller is used to ensure proper data hand - off between the host and ad9737a / AD9739A internal digital clock domains. the circuit shown in figure 160 functions as a delay lock loop in which a 90 phase shifted version of the dci clock input is used to sample the input data into the ddr receiver registers. this ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched dci and dbx[13:0] delays). note that, because the dci delay and sample delay clocks are derived from the div - by - 4 circuitry, this 90 phase relationship holds as long as the delay settings (that is, dc i_del in register 0x13 and register 0x14, and smp_del in reg i ster 0x11 and register 0x12 ) are also matched. db0[13:0] and db1[13:0] dci t valid t valid + t guard 2 1 /f dac max skew + jitter 09616-079 figure 159 . lvds data port timing requirements c
ad9737a/AD9739A data sheet rev. | page 50 of 64 fine delay ddr ff dbx[13:1] data receiver controller dci delay sample delay dci pre post sample dci window pre dci window post dci window sample data to core delay delay fine delay fine delay state machine/ tracking loop elastic fifo ddr ff ddr ff ddr ff ddr ff 180 0 f dac div-by-4 90 270 delay delay ddr ff ddr ff dci delay path sample delay path dco 09616-080 figure 160 . top level diagram of the data receiver controller the div - by - 4 circuit generates four clock phases that serve as inputs to the data receiver controller. all ddr registers in the data and dci paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0 and 90) corresponding to the positive edge of each path are shown. one of the div - by - 4 phases is used to generate the dco signal; therefore, the phase relationship between dco and clocks fed into the controller remains fixed. note that it is this attribu te that allows possible factory calibration of images and clock spurs that are attributed to f dac /4 modulation of the critical dac clock. after this data has been successively sampled into the first set of registers, an elastic fifo is used to transfer th e data into the ad9737a / AD9739A clock domain. to track any phase variation continuously between the two clock domains, the data receiver controller should always b e enabled and placed into track mode (register 0x10, bit 1 and bit 0). tracking mode operates cont - inuously in the background to track delay variations between the host and ad9737a / AD9739A clock domains. it does so by ensuring that the dci signal is sampled within a very narrow window defined by two internally generated clocks (that is, pre and pst), as shown in figure 161 . note that proper sampling of the dci signal can also be confirmed by monitoring the status of dci_pre_ph0 (register 0x0c, bit 2) and dci_pst_ph0 (register 0x0c, bit 0). if the delay settings are correct, the state of dci_ pre_ph0 should be 0, and the state of dci_pst_ph0 should be 1. dci fine delay pst fine delay pre fine_del_skew 09616-081 figure 161 . pre - and post - delay sampling diagram the skew or window width (fine_del_skew) is set via register 0x13, bits[3:0], with a maximum skew of approximately 300 ps and resolution of 12 ps. it is recommended that the skew be set to 36 ps (that is, register 0x13 = 0x72) during initialization . note that the skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time. data receiver co ntroller initialization description the data controller should be initialized and placed into track mode as the second step in the spi boot sequence. the following steps are recommended for the initialization of the data receiver controller: 1. set fine_del_s kew to 2 for a larger dci sampling window (register 0x13 = 0x72). note that the default dci_del and smp_del settings of 167 are optimum. 2. disable the controller before enabling (that is, register 0x10 = 0x00). 3. enable the rx controller in two steps: register 0x10 = 0x02 followed by register 0x10 = 0x03. 4. wait 135 k clock cycles. 5. read back register 0x21 and confirm that it is equal to 0x05 to ensure that the dll loop is locked and tracking. 6. read back the dci_del value to determine whether the value falls within a user defined tracking guard band. if it does not, go back to step 2. c
data sheet ad9737a/AD9739A rev. | page 51 of 64 after the controller is enabled during the initial spi boot process (see table 29 ), the controller enters a search mode where it seeks to fin d the closest rising edge of the dci clock (relative to a delayed version of an internal f dac /4 clock) by simultaneously adjusting the delays in the clocks used to register the dci and data inputs. a state machine searches above and below the initial dci_d el value. the state machine first searches for the first rising edge above the dci_del and then searches for the first rising edge below the dci_del value. the state machine selects the closest rising edge and then enters track mode. it is recommended that the default midpoint delay setting (that is, decimal 167) for the dci_del and smp_del bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for tracking timing variations and preventing the controller from falling out of lock. the adjustable delay span for these internal clocks (that is, dci and sample delay) is nominally 4 ns. the 10 - bit delay value is user programmable from the decimal equivalent code (0 to 384) with approximately 12 p s/lsb resolution via the dci_del (register 0x13 and register 0x14) and smp_del registers (register 0x 11 and register 0x1 2 ). when the controller is enabled, i t overwrites these registers with the delay value it converges upon. the minimum difference between this delay value and the minimum/maximum values (that is, 0 and 384) represents the guard band for tracking. therefore, if the controller initially converges upon a dci_del and smp_del value between 80 and 3044, the controller has a guard band of at least 80 code (approximately 1 ns) to track phase variations between the clock domains. o n initialization of the ad9737a / AD9739A , a certain period of time is required fo r the data receiver controller to establish a lock of the dci clock signal. note that, due to its dependency on the mu controller, the data receiver controller should be enabled only after the mu controllers have been enabled and established lock. all of t he internal controllers operate at a submultiple of the dac update rate. the number of f dac clock cycles required to lock onto the dci clock is typically 70 k clock cycles but can be up to 135 k clock cycles. during the spi initialization process , the user has the option of polling register 0x21 (bit 0, bit 1, and bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into track mode before completing the boot sequence. alternatively, the appropriate irq bit (register 0 x03 and register 0x04) can be enabled such that an irq output signal is generated upon the controller establishing lock. the data receiver controller can also be configured to generate an interrupt request (irq) upon losing lock. losing lock can be caused by disruption of the main dac clock input or loss of a power supply rail. to service the interrupt, the host can poll the rcvr_lck bit (bit 0, recister 0x21) to determine the current state of the controller. if this bit is cleared, the search/track proced ure can be restarted by setting the rcvr_loop_on bit (bit 1) in register 0x10. after waiting the required lock time, the host can poll the rcvr_lck bit to see if it has been set. before leaving the interrupt routine, the rcvr_flg_rst bit (bit 2, register 0 x10) should be reset by writing a high followed by a low. lvds driver and receiver input the ad9737a / AD9739A feature an lvds - compatible driver and receivers. the lvds driver output used for the dco signal includes an equivalent 200 source resistor that limits its nominal output voltage swing to 200 mv when driving a 100 load. the dco output driver can be powered down via register 0x 0 1, bit 5. an equivalent circuit is shown in figure 162 . dco_n vss vdd33 dco_ p v+ v+ v? v? 100 ? vcm 100 ? esd esd 09616-082 figure 162 . equivalent lvds output vss vdd33 dci_ p dbx[13:0] p dci_n dbx[13:0]n 100 ? esd esd 09616-083 figure 163 . AD9739A equivalent lvds input c
ad9737a/AD9739A data sheet rev. | page 52 of 64 t he lvds receivers include 100 termination resistors, as shown in figure 163 . these receivers meet the ieee - 1596.3 - 1996 reduced swing specification (with the exception of input hysteresis , which cannot be guaranteed over all process corners ). figure 164 and table 26 show an example of nominal lvds voltage levels seen at the input of the differential receiver with resulting common - mode voltage and equivalent logic level. note that the ad9737a / AD9739A lvds inputs do not include fail - safe capability; hence, any unused input should be biased with an external circuit or static driver. the lvds receivers can be powered - down via register 0x 01, bit 4. l vds inputs (no fail-safe) v p l vds receiver gnd 100 ? v n v p ,n v com = (v p + v n )/2 logic bit equi v alent v p v n v p v n example 1.4v 1.0v 0.4v ?0.4v 0v logic 1 logic 0 09616-084 figure 164 . lvds data input levels table 26 . example of lvds input levels applied voltages resulting differential voltage resulting common- mode voltage logic bit binary equivalent v p v n v p, n v com 1.4 v 1.0 v +0.4 v 1.2 v 1 1.0 v 1.4 v ? 0.4 v 1.2 v 0 1.0 v 0.8 v +200 mv 900 mv 1 0.8 v 1.0 v ? 200 mv 900 mv 0 mu controller a delay lock loop (dll) is used to optimize the timing between the internal digital and analog domains of the ad9737a / AD9739A such that data is successfully transferred into the txdac core at rates of up to 2.5 gsps. as shown in figure 165 , the dac clock is split into an analog and a digital path with the critical analog path leading to the dac core (for minimum jitter degradation) and the digital path leading to a programmable delay line. note that the output of this delay line serves as the master internal digital clock from which all other internal and external digital clocks are derived. the amount of delay added to this path is under the control of the mu controller, which optimizes the timing between these two clock domains and continuously tracks any variation (once in track mode) to ensure proper data hand - off. 14-bit data 14-bit data ioutp ioutn digital circuitry analog circuitry mu delay dac clock phase detector mu delay controller 09616-085 figure 165 . ad97339a mu delay controller block diagram the mu controller adjusts the timing relationship between the digital and analog domains via a t apped digital delay line having a nominal total delay of 864 ps. the delay value is programmable to a 9 - bit resolution (that is, 0 to 432 decimal) via the mudel bit s (register 0x27 and 0x28) , resulting in a nominal resolution of 2 ps/lsb. because a time de lay maps to a phase offset for a fixed clock frequency, the control loop essentially compares the phase relationship between the two clock domains and adjusts the phase (that is, via a tapped delay line) of the digital clock such that it is at the desired fixed phase offset (set_phs) from the critical analog clock. 0 2 4 6 8 10 12 14 16 18 0 40 80 120 160 200 240 280 320 360 400 440 search starting location guard band guard band mu delay mu phase desired phase 09616-086 figure 166 . typical mu phase characteristic plot at 2.4 gsps figure 166 maps the typical mu phase characteristic at 2.4 gsps v s. the 9 - bit digital delay setting (mudel). the mu phase scaling is such that a value of 16 corresponds to 180 degrees. the critical keep - out window between the digital and analog domains occurs at a value of 0 (but can extend out to 2 depending on the clo ck rate). the target mu phase (and slope) is selected to provide optimum ac performance while ensuring that the mu controller for any device can establish and maintain lock. for example, although a slope and phase setting of ? 6 is considered optimum for op eration between 1.6 gsps and 2.5 gsps, other values are required below 1.6 gsps. c
data sheet ad9737a/AD9739A rev. | page 53 of 64 0 2 4 6 8 10 12 14 16 18 0 40 80 120 160 20 0 240 280 32 0 360 400 440 delay line tap mu phase nom_p1 slow_p1 fast_p1 09616-05 0 figure 167 . mu phase characteristics of three devices from different process lots at 1.2 gsps the mu phase characteristics can vary significantly a mong devices due to g m variations in the digital delay line that are sensitive to process skews , along with temperature and supply. as a result, careful selection of the target phase location is required such tha t the mu controller can converge upon this p hase location for all devices. figure 167 shows th e m u phase characteristics of three devices at 25c from slow, nominal, and fast skew lots at 1.2 gsps. no te t hat a ?6 mu phase setting does not map to any delay li ne tap setting for the fast process skew case ; therefore , another target mu phase is recommended at this clock rate. table 27 provides a list of recommended mu phase/slope settings over the specified clock range o f the ad9737a / AD9739A based on the considerations previously described. these values should be used to ensure robust operation of the mu controller. table 27 . recommended target mu phase settings vs . clock rate clock rate (gsps) slope m u phase 0.8 ? 6 0.9 ? 4 1.0 + 5 1.1 + 8 1.2 + 12 1.3 ? 12 1.4 ? 10 1.5 ? 8 1.6 to 2.5 ? 6 after the mu controller completes its search and establishe s lock on the target mu phase, it attempts to maintain a constant timing relationship between the two clock domains over the specified temperature and supply range. if the mu controller requests a mu delay setting that exceeds the tapped delay line range (that is, <0 or >432), the mu controller can lose lock, causing possible system disruption (that is, can generate an irq or restart the search). to avoid this scenario, symmetrical guard bands are recommended at each end of the mu delay range. the guard ba nd scaling is such that one lsb of guard[4:0] (register 0x29) corresponds to eight lsbs of mudel [8:0] (register 0x28) . the recommended guard band setting of 11 (that is, register 0x29 = 0xcb) corresponds to 88 lsbs, thus providing sufficient margin. mu con troller initialization description the mu controller must be initialized and placed into track mode as a first step in the spi boot sequence. the following steps are required for initialization of the mu controller. note that the ad9737a / AD9739A data sheet specifications and characterization da ta are based on the following mu controller settings: 1. turn on the phase detector with boost (register 0x24 = 0x30). 2. enable t he mu delay controller duty - cycle correction circuitry and specify the recommended slope for phase. (that is, register 0x25 = 0x80 corresponds to a negative slope). 3. specify search/track mode with a recommended target phase, set_phs, of 6 (for example) and an initial mudel[8:0] setting of 216 (register 0x27 = 0x4 6 and register 0x28 = 0x6c). 4. set search tolerance to exact , and retry if the search fails its initial attempt. also, set the guard band to the recommended setting of 11 (register 0x29 = 0xcb). 5. set th e mu controller tracking gain to the recommended setting and enable the mu controller state machine (register 0x26 = 0x03). on completion of the last step, the mu controller begins a search algorithm that starts with an initial delay setting specified by t he mudel bits (that is, 216, which corresponds to the midpoint of the delay line). the initial search algorithm works by sweeping through different mu delay values in an alternating manner until the desired phase (that is, a set_phs of 4) is exactly measur ed. when the desired phase is measured, the slope of the phase measurement is then calculated and compared against the specified slope (slope = negative). if everything matches, the search algorithm is finished. if not, the s earch continues in both directi ons until an exact match is found or a programmable guard band is reached in one of the directions . when the guard band is reached, the search still co ntinues but only in the opposite direction. if the desired phase is not found before the guard band is re ached in the second direction, the search changes back to the alternating mode and continues looking within the guard band. the typical locking time for the mu controller is approximately 180 k dac cycles (at 2 gsps ~ 75 s). the search fails if the mu de lay controller reaches the endpoints . the mu controller can be configured to retry (register 0x29, bit 6) the search or stop. for applications that have a micro - controller, the preferred approach is to poll the mu_lkd status bit (register 0x2a, bit 0) aft er the typical locking time has expired. this method lets the system controller check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to register 0x26). c
ad9737a/AD9739A data sheet rev. | page 54 of 64 for applications tha t do not have polling capabilities, the mu controller state machine should be reconfigured to restart the search, such that lock can be re - attempted with system conditions that may have changed and be different, and thus ma y enable the controller to lock . after the mu delay value is found that exactly matches the desired mu phase setting and slope ( for example, 6 with a negative slope ), the mu controller goes into track mode. in this mode, the mu controller makes slight adjustments to the delay value to tra ck any variations between the two clock paths due to temperature, time , and supply variations. two status bits, mu_lkd (register 0x2a, bit 0) and mu_lst (register 0x2a, bit 1) are available to the user to signal the existing status control loop. if the cur rent phase is more than four steps away from the desired phase, the mu_lkd bit is cleared, and if the lock acquired was previously set, the mu_lst bit is set. should the phase deviation return to within three steps, the mu_lkd bit is set again while the mu _lst is cleared. note that this sort of event may occur if the main clock input (that is, dacclk) is disrupted or the mu controller exceeds the tapped delay line range (that is, <0 or >432). if lock is lost, the mu controller has the option of remaining in the tracking loop or resetting and starting the search again via the contrst bit (register 0x29, bit 5). continued tracking is the preferred state because it is the least disruptive to a system in which the ad 9737a / AD9739A temporarily loses lock. the user can poll the mu delay and phase value by first setting the read bit high (register 0x26, bit 3). after the read bit is set, the mudel[8:0] bits and the set_phs[4: 0] bits (register 0x27 and register 0x28) that the controller is currently using can be read. interrupt requests the ad9737a / AD9739A can provid e the host processo r with an interrupt request output signal (irq) that indicates that one or more of the ad9737a / AD9739A internal controllers have achieved lock or lost lock. these controllers include the mu, dat a receiver, and synchronization controllers. the host can then poll the irq status register (register 0x04) to determine which controller has lost lock. the irq output signal is an active high output signal available on pin f 13. if used, its output should be connected via a 10 k? pull - up resistor to vdd33. each irq is enabled by setting the enable bits in register 0x03, which purposely has the same bit mapping as the irq status bit s in register 0x04. note that these irq status bits are set only when the controller transitions from a false to true state. hence, it is possible for the x_lck_irq and x_lst_irq status bits to be set when a controller temporarily loses lock but is able to reestablish lock before the irq is serviced by the host. in this case, the host should validate the present status of the suspect controller by reading back its current status bits, which are available in register 0x21 and/or register 0x2a. based on the status of these bits, the host can take appropr iate action, if required, to reestablish lock. to clear an irq after servicing, it is necessary to reset relevant bits in register 0x03 by writing 0 followed by another write of 1 to reenable. a detailed diagram of the interrupt circuitry is shown in figure 168. int(n) q d int source spi isr read data (pin f13) spi write int source spi address dat a = 1 imr sclk spi dat a 09616-087 figure 168 . interrupt request circuitry it is also possible to use the irq during the ad9737a / AD9739A initialization phase after power - up to determine when the mu and data receiver controllers have achieved lock. for example, before enabling the mu controller, the mu_lck_en bit can be set and the irq output signal monitored to determine when lock has been established before continuing in a similar manner with the data receiver controllers. note that the relevant lck bit should be cleared before continuing to the next controller. after all controllers are locked, the lost lock enable bits (that is, x_lst_en) should be set. table 28 . interrupt request registers address (hex) bit description 0x03 3 mu_lst_en 2 mu_lck_en 1 rcv_lst_en 0 rcv_lck_en 0x04 3 mu_lst_irq 2 mu_lck_irq 1 rcv_lst_irq 0 rcv_lck_irq 0x21 3 rcvr_trk_on 1 rcvr_lst 0 rcvr_lck 0x2a 1 mu_lst 0 mu_lkd c
data sheet ad9737a/AD9739A rev. | page 55 of 64 analog interface con siderations analog modes of operation the ad9737a / AD9739A use the quad - switch architecture shown in figure 169 . the quad - switch architecture masks the code - dependent glitches that occur in a conventional two - switch dac. figure 170 compares the waveforms for a conventional dac and the quad - switch dac. in the two - switch architecture, a code - dependent glitch occurs each time the dac switches to a different state (that is, d1 to d2). this code - dependent glitching causes an increased amount of dist ortion in the dac. in quad - switch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the code - dependent glitches. however, a constant glitch occurs at 2 dacclk _x because hal f the internal switch es change state on the rising dacclk _x edge wh ereas the other half change state on the falling dacclk _x edge. v g 1 vdd ioutp ioutn v g 1 v g 4 v g 3v g 2 dacclk_x clk latches dbx[13:0] v g 2 v g 3 v g 4 09616-088 figure 169 . AD9739A quad - switch architecture input data dacclk_x two-switch dac output four-switch dac output (normal mode) t d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 09616-089 fig ure 170 . two - switch and quad - switch dac waveforms another attribute of the quad - switch architecture is that it also enables the dac core to operate in one of the following two modes: normal mode and mix - mode . the mode is selected v ia spi register 0x08, bits[1:0] , with normal mode being the default value. in the mix - mode , the output is effectively chopped at the dac sample rate. this has the effect of reducing the power of the fundamental signal while increasing the power of the imag es centered around the dac sample rate, thus improving the output power of these images. input da ta dacc l k_x fo ur -switch dac o utput ( f s mix mode) ?d 6 ?d 7 ?d 8 ?d 9 ?d 10 d 6 d 7 d 8 d 9 d 10 ?d 1 ?d 2 ?d 3 ?d 4 ?d 5 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 09616-090 figure 171 . mix - mode dac waveforms figure 171 shows the dac waveforms for mix - mode . this ability to change modes provides the user the flexibility to place a carrier anywhere in the first two nyquist zones, depending on the operating mode selected. switching between the analog modes reshapes the sinc roll - off that is inherent at the dac output . the maximum amplitude in both nyquist zones is impacted by this sinc roll - off, depending on where the carrier is placed (see figure 172 ). as a practical matter, the usable bandwidth in the third nyquist zone becomes lim ited at higher dac clock rates (that is, >2 gsps) when the output bandwidth of the dac core and the interface network (that is, balun) contributes to additional roll - off. freque nc y (hz) 0fs 1. 50 fs 1. 25 fs 1. 00 fs 0. 75 fs 0. 50 fs 0. 25 fs ?3 5 ?3 0 ?2 5 ?2 0 ?1 5 ?1 0 ?5 0 first nyquist zone second nyquist zone third nyquist zone mix mode normal mode 09616-091 figure 172 . sinc roll - off for each analog operating mode c
ad9737a/AD9739A data sheet rev. | page 56 of 64 clock input considerations d d q v cc v ee v t q v ref 50? 50? 50? 50? 50? dacclk_ p dacclk_n 100? 10nf 10nf adclk914 ad9737a/ad9739 a 10nf 10nf 50? 09616-092 figure 173 . adclk914 interface to the ad9737a / AD9739A clk i nput vco pll adf4350 fref 1.8v p-p v vco 1nf 1nf 3.9nh rf out a? rf out a+ rf out a? rf out a+ 100? dacclk_p dacclk_n div-by-2 n n = 0 ? 4 09616-093 ad9737a/ad9739 a figure 174 . adf4350 interface to the ad9737a / AD9739A clk input the quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. the phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. it can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 log10(f out /f clk ) when the dac clock path contribution, along with thermal and quantization effects, are negligible. the ad9737a / AD9739A clock receiver provides optimum jitter performance when dr iven by a fast slew rate originating from the lvpecl or cml output drivers. for a low jitter sinusoidal clock source, the adclk914 can be used to square - up the signal and provide a cml input signal for the ad9737a / AD9739A clock receiver. note that all specifications and characterization presented in the data sheet are with the adclk914 driven by a high quality rf signal generator with the clock receiver biased at an 800 mv level. figure 174 shows a clock source based on the adf4350 lo w phase noise/jitter pll. the adf4350 can provide output frequencies from 140 mhz up to 4.4 ghz with jitter as low as 0.5 ps rms. each single - ended output can provide a squared - up output level that can be vari ed from ?4 dbm to +5 dbm , allowing for >2 v p - p output differential swings. the adf4350 also includes an additional cml buffer that can be used to drive another ad9737a / AD9739A device. esd dacclk_ p dacclk_n vddc vssc clkx_offset dir_x = 0 clkx_offset di r_x = 0 4-bit pmos iout arr ay 4-bit nmos iout arr ay 09616-094 figure 175 . clock input and common - mode control c
data sheet ad9737a/AD9739A rev. | page 57 of 64 the ad9737a / AD9739A clock receiver features the ability to independently adjust the common - mode level of its inputs over a span of 100 mv centered about i t s mid - supply point (that is, vddc/2) , as well as an offset for hysteresis purposes. figure 175 s hows the equivalent input circuit of one of the inputs. esd diodes are not shown for clarity purposes. it has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 v. this can be achieve d by writing a 0x0f (corresponding to a ?15) setting to both cross controller registers (that is, register 0x22 and register 0x23). 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 11 13 15 offset code common mode (v) clkp clkn 09616-095 figure 176 . common - mode voltage with respect to clkp_offset/clkn_offset and dir_p/dir_n voltage r eference the ad9737a / AD9739A output current is set by a combination of digital control bits and the i120 reference current, as shown in figure 177 . current scaling fsc[9:0] ad9737a/ad9739 a dac ifull-scale 10k ? 1nf v ref i120 vssa i120 v bg 1.2v + ? 09616-096 figure 177 . voltage reference circuit the reference current is obtained by forcing the band gap voltag e across an external 10 k? resistor from i120 (pin b14) to ground. the 1.2 v nominal band gap voltage (vref) generates a 120 a reference current in the 10 k? resistor. note the following constraints when configuring the voltage reference circuit: x both the 1 0 k? resistor and 1 nf bypass capacitor are required for proper operation. x digitally a djust the dacs output full - scale current, i outfs , from its default setting of 20 ma. x the ad9737a / AD9739A are not a multiplying dac. modulating the reference current, i120, with an ac signal is not supported. x the band gap voltage appearing at the vref pin (pin c14) must be buffered for use with an external circuitry because its out put impedance is approximately 5 k?. x an external reference can be used to overdrive the internal reference by connecting it to the vref pin. i outfs can be adjusted digitally over 8.7 ma to 31.7 ma by using fsc[9:0] (register 0x06 and register 0x07). the foll owing equation relates i outfs to the fsc[9:0] bits , which can be set from 0 to 1023. i outfs = 22.6 fsc[9:0] /1000 + 8.7 (1) note that a default value of 0x200 generates 20 ma full scale, which is used for most of the characterization presented in this dat a sheet (unless noted otherwise). analog outputs equivalent dac output and transfer function the ad9737a / AD9739A provide complementary current outputs, ioutp and i outn, that source current into an external ground reference load. figure 178 shows an equivalent output circuit for the dac. note that, compared to most current output dacs of this type, the ad9737a / AD9739A outputs exhibit a slight offset current (that is, i outfs /16), and the peak differential ac current is slightly below i outfs /2 (that is, 15/32 i outfs ). 17/32 i outfs i peak = 15/32 i outfs ac 70 ? 2.2pf i outfs = 8.6 ? 31.2m a 17/32 i outfs 09616-097 figure 178 . equivalent dac output circuit as shown in figure 178 , the dac output can be modeled as a pair of dc current sources that source a current of 17/32 i outfs to each output. a differential ac cu rrent source, i peak, is used to model the signal - dependent nature of the dac output. the polarity and signal dependency of this ac current source are related to the digital code by the following equation: f ( code ) = ( daccode ? 819 2)/8192 (2) ? 1 < f ( code ) < 1 (3) where daccode = 0 to 16,383 (decimal). because i peak can swing (15/32) i outfs , the output currents measured at ioutp and ioutn can span from i outfs /16 to i outfs . however, because the ac signal - dependent current com ponent is complementary, the sum of the two outputs is always constant (that is, ioutp + ioutn = (34/32) i outfs ). c
ad9737a/AD9739A data sheet rev. | page 58 of 64 the code - dependent current measured at the ioutp and ioutn output s is as follows: ioutp = 17/32 i outfs + 15/32 i outfs f ( code ) (4) iou tn = 17/32 i outfs ? 15/32 i outfs f ( code ) (5) figure 179 shows the ioutp vs. daccode transfer function when i outfs is set to 19.65 ma. 20 18 10 12 14 16 output current (ma) 8 6 4 2 0 0 4096 8192 12,288 dac code 16,384 09616-098 figure 179 . gain curve for fsc[9:0] = 512, dac offset = 1.228 ma pe ak dac output power capability the maximum peak power capability of a differential current output dac is dependent on its peak differential ac current, i peak , and the equivalent load resistance it sees. because the ad9737a / AD9739A include a differential 70 resistance, it is best to use a doubly terminated external output network similar to what is shown in figure 181 . in this case, the equivalent load seen by the ac current source of the dac is 25 . if the ad9737a / AD9739A are programmed for i outfs = 20 ma, the peak ac current is 9.375 ma and the peak power delivered to the equivalent load is 2.2 mw (that is, p = i 2 r). because the sourc e and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mw or 0.4 dbm. to calculate the rms power delivered to the load, the following must be considered: ? peak - to - rms of th e digital waveform ? any digital backoff from digital full scale ? the dacs sinc response and nonideal losses in external network for example, a reconstructed sine wave with no digital backoff ideally measures ?2.6 dbm because it has a peak - to - rms ratio of 3 db. if a typical balun loss of 0.4 dbm is included, ?3 dbm of actual power can be expected in the region where the sinc response of the dac has negligible influence. increasing the output power is best accomplished by increasing i outfs , although any degrad ation in linearity performance must be considered acceptable for the target application. i peak = 15/32 i outfs ac 70 ? i outfs = 8.6 ? 31.2m a 180 ? r load = 50 ? r source ? lossless balun 1:1 09616-099 figure 180 . equivalent circuit for determining maximum peak power to a 50 load c
data sheet ad9737a/AD9739A rev. | page 59 of 64 output stage configuration the ad9737a / AD9739A are intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, docsis cmts) and/or high if/rf signal generation. optimum ac performance can be realized only if the dac output is configured for differential (that is, balanced) operation with its output common - mode voltage biased to analog ground. the output network used to interface to the dac should provide a near 0 dc bias path to analog ground. any imbalance in the output impedance between the ioutp and ioutn pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. com ponent selection and layout are critical in realizing the performance potential of the ad9737a / AD9739A . mini-circuits ? tc1-33-75g+ 90? 90? ioutp ioutn 70? 09616-100 figure 181 . recommended balun for wideband applications with upper bandwidths of up to 2.2 ghz most applications requiring balanced - to - unbalanced conversion can take advantage of the ruthroff 1:1 balun configuration shown in figure 181 . this conf iguration provides excellent amplitude/phase balance over a wide frequency range while providing a 0 dc bias path to each dac output. also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction o f up to 2.2 ghz. the characterization plots shown in this data sheet are based on the ad9737a / AD9739A evaluation board, which uses this configuration. figure 182 compares the measured frequency response for normal and mix - mode using the ad9737a / AD9739A evaluation board vs. the ideal frequency response. ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 power (dbc) ?12 ?9 ?6 ?3 0 0 500 1000 1500 2000 2500 3000 3500 frequenc y (mhz) ideal baseband mode mix mode tc1-33-75g baseband tc1-33-75g ideal mix mode 09616-101 figure 182 . measured vs. ideal frequency response for normal (baseband) and mix - mode operation using a tc1 - 33- 75g transformer on the ad9737a / AD9739A evb figure 183 shows an interface that can be considered when interfacing the dac output to a self - biased differential gain block. the inductors shown serve as rf chokes (l) that provide the dc bias path to analog ground. the value of the inductor, along with the dc blocking capacitors (c), determines the lower cutoff frequency of the composite pass - band response. an rf balun should also be considered before the rf differential ga in stage and any filtering to ensure symmetrical common - mode impedance seen by the dac output while suppressing any common mode noise, harmonics, and clock spurs prior to amplification. 90? ioutp ioutn 70? l l rf diff amp c c optional balun and filter 90? lpf 09616-102 figure 183 . interfacing the dac output to t he self - biased differential gain stage for applications operating the ad9737a / AD9739A in mix - mode with output frequencies extending beyond 2.2 ghz, the circuits s hown in figure 184 should be considered. the circuit in figure 184 uses a wideband balun with a configuration similar to the one shown in figure 183 to provide a dc bias path for the dac outputs. the circuit in figure 185 takes advantage of cerami c chip baluns to provide a dc bias path for the dac outputs while providing excellent amplitude/phase balance over a narrower rf band. these low cost, low insertion loss baluns are available for different popular rf bands and provide excellent amplitude/ phase balance over their specified frequency range. c c mini-circuits tc1-1-462m 90? ioutp ioutn 70? l l 90? 09616-103 figure 184 . recommended mix - mode configuration offering extended rf bandwidth using a tc1 -1- 43a+ balun murata johanson technology chip baluns 180? ioutp ioutn 70? 09616-104 figure 185 . lowest cost and size configuration for narrow rf band operation c
ad9737a/AD9739A data sheet rev. | page 60 of 64 nonideal spectral artifacts the ad9737a / AD9739A output spectrum contains spectral artifacts that are not part of the original digital input waveform. th ese nonideal artifacts include harmonics (including alias harmonics), images, and clock spurs. figure 186 shows a spectral plot of the ad9737a / AD9739A within the first nyquist zone (that is, dc to f dac /2 ) reconstructing a 650 mhz, 0 dbfs sine wave at 2.4 gsps. besides the desired fundamental tone at the ? 7.8 dbm level, the spectrum also reveals these nonideal artifacts that also appear as spurs above the measurement noise floor. because these nonideal artifacts are also evident in the second and third nyquist zones during mix - mode operation, the effects of these artifacts should also be considered when selecting the dac clock rate for a target rf band. 09616-105 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 200 400 600 800 1000 1200 power (dbc) frequenc y (mhz) hd3 hd5 hd9 hd6 hd4 fund at ?7.6dbm f dac /4 ? f out f dac /2 ? f out f dac /4 3/4 f dac /4 ? f out hd2 figure 186 . spectral plot note the following important observations pertaining to these nonideal spectral artifacts: 1. a full - scale sine wave (that is, single - tone) typically represents the worst case condition because it is has a peak - to - rms ratio of 3 db and is unmodulated. harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs . significant characterization of a high speed dac is performed using single (or multitone) signals for this reason. 2. modulated signals (that is, am, pm, or fm) do not appear as spurs but rather as signals whose power spectral density is spread over a defin ed bandwidth determined by the modulation parameters of the signals. any harmonics from the dac spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. for this reason, harmonics often appear as slight b umps in the measurement noise floor and can be difficult to discern . 3. images appear as replicas of the original signal, hence, can be easier to identify. in the case of the ad9737a / AD9739A , internal modulation of the sampling clock at intervals related to f dac /4 generate image pairs a t ? f dac , ? f dac , and ? f dac . both upper and lower sideband images associated with ? f dac fall within the first nyquist zone, whereas only the lower image of ? f dac and ? f dac fall back. note that the lower images appear frequency inverted. the ratio between the fundamental and various images (that is, dbc) remains mostly signal independent because the mechanism causing thes e images is related to corruption of the sampling clock. 4. the magnitude of these images for a given device depends on several factors , including dac clock rate, output frequency, and mu controller phase setting. because the image magnitude is repeatable be tween power - up cycles (assuming the same conditions), a one - time factory calibration procedure can be used to improve suppression. calibration consists of additional dedicated dsp resources in the host that can generate a replica of the image with proper a mplitude, phase, and frequency scaling to cancel the image from the dac. because the image magnitude can vary among devices, each device must be calibrated. 5. a clock spur appears at f dac /4 and integer multiples of it. similar to images, the spur magnitude a lso depend s on the same factors that cause variations in image levels. however , unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. the ca libration method is similar to image calibration; however, only a digital tone of equal amplitude and opposite phase at f dac /4 need be generated. 6. a large clock spur also appears at 2 f dac in either normal or mix - mode operation. this clock spur is due to the quad switch dac architecture causing switching events to occur on both edges of f dac . c
data sheet ad9737a/AD9739A rev. | page 61 of 64 lab evaluation of th e ad9737a / AD9739A figure 187 shows a recommended lab setup that was used to characterize the performance of the ad9737a / AD9739A . the dpg2 is a dual port lvds/cmos data patt ern generator that is available from analog devices, inc., with an up to 1.25 gsps data rate. the dpg2 directly interfaces to the ad9737a / AD9739A evaluation board via tyco z - pack hm - zd connectors. a low phase noise/jitter rf source such as an r&s sma100a signal generator is used for the dac clock. a +5 v power supply is used to power up the ad9737a / AD9739A evaluation board, and sma cabling is used to interface to the supply, clock source, and spectrum analyzer. a usb 2.0 interface to a host pc is used to communicate to both the ad 9737a / AD9739A evaluation board and the dpg2. a high dynamic range spectrum analyzer is required to evaluate the ac performance of the ad9737a / AD9739A rec onstructed waveform . this is especially the case when measuring aclr performance for high dynamic range applications such as multicarrier docsis cmts applications. harmonic, sfdr, and imd measurements pertaining to unm odulated carriers can benefit by using a sufficiently high rf attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. however, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range rf amplifier and/or passive filters to measure close - in and wideband aclr performance when using spectrum analyzers of limited dynamic range. adi pattern generator dpg2 ad9739 eval. board rhode and schwartz sma 100a agilent psa e4440a 10 mhz refin 10 mhz reout lab pc usb 2.0 gpib lvds dat a and dci dco 1. 6ghz to 2.5ghz 3dbm power supply +5v 09616-106 figure 187 . lab test setup used to characterize the ad9737a / AD9739A recommended start - up sequence o n power - up of the ad9737a / AD9739A , a host processor is required to initialize and configure the ad9737a / AD9739A via its spi port. figure 188 shows a flowc hart o f the sequential steps required . table 29 provides more detail on the spi register write/read operations required to implement the flowchart steps. note the following: ? a software reset is optional because the ad9737a / AD9739A have both an internal por circuit and a reset pin. ? t he mu controller must be first enabled (and in track mode) before the data receiver controller is enabled because the dco o utput signal is derived from this circuitry. ? a wait period is related to f data periods. ? limit the number of attempts to lock the controllers to three; locks typically occur on the first attempt. ? hardware or software interrupts can be used to monitor the status of the controllers. configure spi port software reset set clk input cmv configure mu cont. wait a few 100s mu cont. locked? yes no yes wait a few 100s no reconfigure txdac from default setting optional configure rx data cont. rx data cont. locked? 09616-107 figure 188 . flowchart for initialization and configuration of the ad9737a / AD9739A c
ad9737a/AD9739A data sheet rev. | page 62 of 64 table 29 . recommended spi initialization step address (hex) write value comments 1 0x00 0x00 configure for the 4 - wire spi mode with msb. note that bits[7:5] must be mirrored onto bits[2:0] because the msb/lsb format can be unknown at power - up. 2 0x00 0x20 software reset to default spi values. 3 0x00 0x00 clear the reset bit. 4 0x22 0x0f set the common - mode voltage of dacclk_p and dacclk_n inputs 5 0x23 0x0f 6 0x24 0x30 configure the mu controller. 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6c 10 0x29 0xcb 11 0x26 0x02 12 0x26 0x03 enable the mu controller search and track mode. 13 wait for 160 k 1/f data cycles. 14 0x2a read back register 0x2a and confirm that it is equal to 0x01 to ensure that the dll loop is lo cked. if it is not locked, return to step 10 and repeat. limit attempts to three before breaking out of the loop and reporting a mu lock failure. 15 ensure that the ad9737a / AD9739A are fed with dci clock input from the data source. 16 0x13 0x72 set fine_del_skew to 2. 17 0x10 0x00 disable the data rx controller before enabling it. 18 0x10 0x02 enable the data rx controller for loop and irq. 19 0x10 0x03 enab le the data rx controller for search and track mode. 20 wait for 135 k 1/f data cycles. 21 0x21 read back register 0x21 and confirm that it is equal to 0x09 to ensure that the dll loop is locked and tracking. if it is not locked and tracking, return to step 16 and repeat. limit attempts to three before breaking out of the loop and reporting an rx data lock failure. 22 0x06 0x07 0x00 0x02 optional: modify the txdac i outfs setting (the default is 20 ma). 23 0x08 0x00 optional: modify the txdac operation mode (the default is normal mode). c
data sheet ad9737a/AD9739A rev. c | page 63 of 64 outline dimensions 12.10 12.00 sq 11.90 0.43 max 0.25 min 1.00 max 0.85 min a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 9 5 4 1.40 max 0.55 0.50 0.45 10.40 bsc sq 11-18-2011-a compliant with jedec standards mo-275-ggaa-1. coplanarity 0.12 ball diameter 0.80 bsc detail a a1 ball corner a1 ball corner detail a bottom view top view seating plane figure 189. 160-ball chip scale package ball grid array [csp_bga] (bc-160-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9737abbcz ?40c to +85c 160-ball chip scale package ball grid array [csp_bga] bc-160-1 ad9737abbczrl ?40c to +85c 160-ball chip scale package ball grid array [csp_bga] bc-160-1 ad9737a-ebz evaluation board for norm al, cmts, and mix-mode evaluation AD9739Abbcz ?40c to +85c 160-ball chip scale package ball grid array [csp_bga] bc-160-1 AD9739Abbczrl ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc-160-1 AD9739A-ebz evaluation board for norm al, cmts, and mix-mode evaluation AD9739A-fmc-ebz evaluation board with fmc connector for xilinx based fpga development platforms 1 z = rohs compliant part.
ad9737a/AD9739A data sheet rev. c | page 64 of 64 notes ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09616-0-2/12(c)


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